CS5165A datasheet(6/18 Pages) ONSEMI | 5−Bit Synchronous CPU Buck Controller

6 page

CS5165A

http://onsemi.com

PACKAGE PIN DESCRIPTION

PACKAGE PIN #

SOIC−16

PIN SYMBOL

FUNCTION

1, 2, 3, 4, 6

VID0−VID4

Voltage ID DAC input pins. These pins are internally pulled up to 5.0 V if left open. VID4 selects

the DAC range. When VID4 is high (logic one), the Error Amp reference range is 2.14 V to 3.45 V

with 100 mV increments. When VID4 is low (logic zero), the Error Amp reference voltage 1.34 V

to 2.09 V with 50 mV increments.

Soft−Start Pin. A capacitor from this pin to LGND sets the Soft−Start and fault timing.

COFF

Off−Time Capacitor Pin. A capacitor from this pin to LGND sets both the normal and extended off

time.

ENABLE

Output Enable Input. This pin is internally pulled up to 1.8 V. A logic Low (< 0.8) on this pin

disables operation and places the CS5165A into a low current sleep mode.

VCC

Input Power Supply Pin.

GATE(H)

High Side Switch FET driver pin.

PGND

High current ground for the GATE(H) and GATE(L) pins.

GATE(L)

Low Side Synchronous FET driver pin.

PWRGD

Power Good Output. Open collector output drives low when VFB is out of regulation. Active when

ENABLE input is low.

LGND

Reference ground. All control circuits are referenced to this pin.

COMP

Error Amp output. PWM Comparator reference input. A capacitor to LGND provides Error Amp

compensation.

VFB

Error Amp, PWM Comparator, and Low VFB Comparator feedback input.

Figure 2. Block Diagram

ENABLE

VID0

VID1

VID2

VID3

VID4

VFB Low

Comparator

PWRGD

LGND

PWM

Comparator

SS Low

Comparator

SS High

Comparator

VCC Monitor

Error Amplifier

VCC1

VCC

COFF

VGATE(H)

VGATE(L)

PGND

FAULT

Latch

PGND

Latch

PWM

COFF

One Shot

Off−Time

Timeout

Edge Triggered

Extended

Off−Time

Timeout

Normal

Off−Time

Timeout

Maximum

On−Time

Timeout

GATE(H) = ON

GATE(H) = OFF

2.0

5.0 V

0.7 V

2.5 V

1.0 V

3.95 V

3.87V

VFB

COMP

PWM COMP

−

VCC

Time−Out

Timer

(30

ms)

Enable

Comparator

Circuit Bias

−8.5%

+8.5%

−

+−

−

1.25 V

20 k

7.0

5 BIT

DAC

Delay

Blanking

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