ADM1067

Rev. B | Page 8 of 32

Pin Number

LFCSP1

TQFP

Mnemonic

Description

38

45

MDN

Digital Input. Forces DACs to their highest value, causing the voltage at the feedback node to rise.

This is compensated for by a decrease in the supply output voltage, thus margining down.

39

46

VDDCAP

Device Supply Voltage. Linearly regulated from the highest of the VPn, VH pins to a typical of 4.75 V.

Note that the capacitor must be connected between this pin and GND. A 10 μF capacitor is

recommended for this purpose.

40

47

GND2

Supply Ground.