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NB3N3001 Datasheet(PDF) 1 Page - ON Semiconductor |
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NB3N3001 Datasheet(HTML) 1 Page - ON Semiconductor |
1 / 8 page © Semiconductor Components Industries, LLC, 2006 October, 2006 − Rev. 1 1 Publication Order Number: NB3N3001/D NB3N3001 3.3 V 106.25 MHz/ 212.5 MHz PureEdge Clock Generator with LVPECL Differential Output Description The NB3N3001 is a low−jitter, dual−rate PLL−synthesized clock generator. It accepts a standard 26.5625 MHz fundamental mode AT cut parallel resonant crystal as the reference source for its integrated crystal oscillator and low noise phase−locked loop (PLL) and produces user selectable clock frequencies of either 106.25 MHz or 212.5 MHz. In addition, the PLL circuitry will generate a 50% duty cycle square−wave through a pair of differential LVPECL clock outputs. Typical phase jitter at 106.25 MHz is 0.3 ps RMS from 637 kHz to 10 MHz. The LVPECL output drivers can be disabled to high impedance with the OE pin set LOW. The NB3N3001 operates from a single +3.3 V supply, and is available in both plastic package and die form. The operating temperature range is from −40 °C to +85°C. The NB3N3001 device provides the optimum combination of low cost, flexibility, and high performance which makes it ideal for Fibre−Channel applications. Features • PureEdge Clock Family Provides Accuracy and Precision • Selectable Output Frequency of 106.25 MHz or 212.5 MHz • Crystal Oscillator Interface Designed for a 26.5625 MHz Crystal • Fully Integrated Phase−Lock−Loop with Internal Loop Filter • Differential 3.3 V LVPECL Outputs • Exceeds Bellcore and ITU Jitter Generation Specification • RMS Phase Jitter @ 106.25 MHz, using a 26.5625 MHz Crystal (637 kHz − 10 MHz): 0.3 ps (Typical) • RMS Phase Noise at 106.25 MHz Phase Noise: Offset Noise Power 100 Hz −108 dBc/Hz 1 kHz −122 dBc/Hz 10 kHz −135 dBc/Hz 100 kHz −135 dBc/Hz • Operating Range: VCC = 3.135 V to 3.465 V • −40°C to +85°C Ambient Operating Temperature • Small Footprint 8−pin TSSOP Package • This is a Pb−Free Device Figure 1. Logic Diagram Phase Detector Charge Pump N = B8 or B4 M = B32 Crystal Oscillator Q Q XIN XOUT VCO 850 MHz 26.5625 MHz LVPECL Output 212.5 MHz or 106.25 MHz FSEL MARKING DIAGRAM A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package TSSOP−8 DT SUFFIX CASE 948S http://onsemi.com See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. ORDERING INFORMATION 301 YWW A G |
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