ADP3110A

Rev. 0 | Page 5 of 16

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DRVH

8

SW

7

PGND

6

DRVL

5

ADP3110A

TOP VIEW

(Not to Scale)

Figure 2. Pin Configuration

Table 3. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

BST

Upper MOSFET Floating Bootstrap Supply. A capacitor connected between the BST and SW pins holds this

bootstrapped voltage for the high-side MOSFET while it is switching.

2

IN

Logic Level PWM Input. This pin has primary control of the driver outputs. In normal operation, pulling this pin

low turns on the low-side driver; pulling it high turns on the high-side driver.

3

OD

Output Disable. When low, this pin disables normal operation, forcing DRVH and DRVL low.

4

VCC

Input Supply. This pin should be bypassed to PGND with ~1 μF ceramic capacitor.

5

DRVL

Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET.

6

PGND

Power Ground. Connect this pin closely to the source of the lower MOSFET.

7

SW

Switch Node Connection. This pin is connected to the buck-switching node, close to the upper MOSFET source.

It is the floating return for the upper MOSFET drive signal. It is also used to monitor the switched voltage to

prevent the lower MOSFET from turning on until the voltage is below ~1 V.

8

DRVH

Buck Drive. Output drive for the upper (buck) MOSFET.