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ADSP-BF534WBBCZ-4B Datasheet(PDF) 3 Page - Analog Devices |
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ADSP-BF534WBBCZ-4B Datasheet(HTML) 3 Page - Analog Devices |
3 / 68 page ADSP-BF534/ADSP-BF536/ADSP-BF537 Rev. B | Page 3 of 68 | July 2006 GENERAL DESCRIPTION The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors are members of the Blackfin family of products, incorporating the Analog Devices/Intel Micro Signal Architecture (MSA). Blackfin processors combine a dual-MAC state-of-the-art signal processing engine, the advantages of a clean, orthogonal RISC- like microprocessor instruction set, and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction-set architecture. The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors are completely code and pin compatible. They differ only with respect to their performance, on-chip memory, and presence of the Ethernet MAC module. Specific performance, memory, and feature configurations are shown in Table 1. By integrating a rich set of industry-leading system peripherals and memory, the Blackfin processors are the platform of choice for next-generation applications that require RISC-like pro- grammability, multimedia support, and leading-edge signal processing in one integrated package. PORTABLE LOW POWER ARCHITECTURE Blackfin processors provide world-class power management and performance. They are produced with a low power and low voltage design methodology and feature on-chip dynamic power management, which is the ability to vary both the voltage and frequency of operation to significantly lower overall power consumption. This capability can result in a substantial reduc- tion in power consumption, compared with just varying the frequency of operation. This allows longer battery life for portable appliances. SYSTEM INTEGRATION The Blackfin processor is a highly integrated system-on-a-chip solution for the next generation of embedded network-con- nected applications. By combining industry-standard interfaces with a high performance signal processing core, cost-effective applications can be developed quickly, without the need for costly external components. The system peripherals include an IEEE-compliant 802.3 10/100 Ethernet MAC (ADSP-BF536 and ADSP-BF537 only), a CAN 2.0B controller, a TWI controller, two UART ports, an SPI port, two serial ports (SPORTs), nine general-purpose 32-bit timers (eight with PWM capability), a real-time clock, a watchdog timer, and a parallel peripheral interface (PPI). BLACKFIN PROCESSOR PERIPHERALS The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors con- tains a rich set of peripherals connected to the core via several high bandwidth buses, providing flexibility in system configura- tion as well as excellent overall system performance (see the block diagram on Page 1). The processors contain dedicated network communication modules and high speed serial and parallel ports, an interrupt controller for flexible management of interrupts from the on-chip peripherals or external sources, and power management control functions to tailor the perfor- mance and power characteristics of the processor and system to many application scenarios. All of the peripherals, except for the general-purpose I/O, CAN, TWI, real-time clock, and timers, are supported by a flexible DMA structure. There are also separate memory DMA channels dedicated to data transfers between the processor’s various memory spaces, including external SDRAM and asynchronous memory. Multiple on-chip buses running at up to 133 MHz provide enough bandwidth to keep the processor core running along with activity on all of the on-chip and external peripherals. The Blackfin processors include an on-chip voltage regulator in support of the processors’ dynamic power management capabil- ity. The voltage regulator provides a range of core voltage levels when supplied from a single 2.25 V to 3.6 V input. The voltage regulator can be bypassed at the user’s discretion. Table 1. Processor Comparison Features Ethernet MAC — 1 1 CAN 1 1 1 TWI 1 1 1 SPORTs 2 2 2 UARTs 2 2 2 SPI 1 1 1 GP Timers 8 8 8 Watchdog Timers 1 1 1 RTC 1 1 1 Parallel Peripheral Interface 1 1 1 GPIOs 48 48 48 Memory Configuration L1 Instruction SRAM/Cache 16K bytes 16K bytes 16K bytes L1 Instruction SRAM 48K bytes 48K bytes 48K bytes L1 Data SRAM/Cache 32K bytes 32K bytes 32K bytes L1 Data SRAM 32K bytes — 32K bytes L1 Scratchpad 4K bytes 4K bytes 4K bytes L3 Boot ROM 2K bytes 2K bytes 2K bytes Maximum Speed Grade 500 MHz 400 MHz 600 MHz Package Options: Sparse Mini-BGA Mini-BGA 208-Ball 182-Ball 208-Ball 182-Ball 208-Ball 182-Ball |
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