DS3181 datasheet(10/389 Pages) MAXIM

Part #	DS3181

Description	Single/Dual/Triple/Quad ATM/Packet PHYs with Built-In LIU

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Manufacturer	MAXIM [Maxim Integrated Products]

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Figure 10-47. Trail Trace Controller Block Diagram ................................................................................................ 188

Figure 10-48. Trail Trace Byte (DT = Trail Trace Data)........................................................................................... 190

Figure 10-49. FEAC Controller Block Diagram........................................................................................................ 191

Figure 10-50. FEAC Codeword Format................................................................................................................... 192

Figure 10-51. Line Encoder/Decoder Block Diagram .............................................................................................. 193

Figure 10-52. B3ZS Signatures ............................................................................................................................... 195

Figure 10-53. HDB3 Signatures............................................................................................................................... 195

Figure 10-54. BERT Block Diagram ........................................................................................................................ 196

Figure 10-55. PRBS Synchronization State Diagram.............................................................................................. 198

Figure 10-56. Repetitive Pattern Synchronization State Diagram........................................................................... 199

Figure 10-57. LIU Functional Diagram..................................................................................................................... 200

Figure 10-58. DS3/E3/STS-1 LIU Block Diagram.................................................................................................... 201

Figure 10-59. Receiver Jitter Tolerance .................................................................................................................. 204

Figure 13-1. JTAG Block Diagram........................................................................................................................... 359

Figure 13-2. JTAG TAP Controller State Machine .................................................................................................. 360

Figure 13-3. JTAG Functional Timing...................................................................................................................... 363

Figure 14-1. DS3184 Pin Assignments—400-Lead BGA........................................................................................ 364

Figure 14-2. DS3183 Pin Assignments—400-Lead BGA........................................................................................ 365

Figure 14-3. DS3182 Pin Assignments—400-Lead BGA........................................................................................ 365

Figure 14-4. DS3181 Pin Assignments—400-Lead BGA........................................................................................ 366

Figure 15-1. Mechanical Dimensions—400-Lead BGA........................................................................................... 367

Figure 15-2. Mechanical Dimensions (continued) ................................................................................................... 369

Figure 18-1. Clock Period and Duty Cycle Definitions............................................................................................. 373

Figure 18-2. Rise Time, Fall Time, and Jitter Definitions ........................................................................................ 373

Figure 18-3. Hold, Setup, and Delay Definitions (Rising Clock Edge) .................................................................... 373

Figure 18-4. Hold, Setup, and Delay Definitions (Falling Clock Edge).................................................................... 374

Figure 18-5. To/From High-Z Delay Definitions (Rising Clock Edge)...................................................................... 374

Figure 18-6. To/From High-Z Delay Definitions (Falling Clock Edge) ..................................................................... 374

Figure 18-7. Micro Interface Nonmultiplexed Read/Write Cycle ............................................................................. 380

Figure 18-8. Micro Interface Multiplexed Read Cycle.............................................................................................. 381

Figure 18-9. E3 Waveform Template....................................................................................................................... 384

Figure 18-10. STS-1 Pulse Mask Template ............................................................................................................ 385

Figure 18-11. DS3 Pulse Mask Template................................................................................................................ 386

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