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DP83848H Datasheet(PDF) 11 Page - National Semiconductor (TI) |
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DP83848H Datasheet(HTML) 11 Page - National Semiconductor (TI) |
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11 / 72 page  11 www.national.com 1.6 Strap Options DP83848H uses many functional pins as strap options. The values of these pins are sampled during reset and used to strap the device into specific modes of operation. The strap option pin assignments are defined below. The functional pin name is indicated in parentheses. A 2.2 k Ω resistor should be used for pull-down or pull-up to change the default strap option. If the default option is required, then there is no need for external pull-up or pull down resistors. Since these pins may have alternate func- tions after reset is deasserted, they should not be con- nected directly to VCC or GND. Signal Name Type Pin # Description PHYAD0 (COL) PHYAD1 (RXD_0) PHYAD2 (RXD_1) PHYAD3 (RXD_2) PHYAD4 (RXD_3) S, O, PU S, O, PD 35 36 37 38 39 PHY ADDRESS [4:0]: The DP83848H provides five PHY ad- dress pins, the state of which are latched into the PHYCTRL reg- ister at system Hardware-Reset. The DP83848H supports PHY Address strapping values 0 (<00000>) through 31 (<11111>). A PHY Address of 0 puts the part into the MII Isolate Mode. The MII isolate mode must be se- lected by strapping Phy Address 0; changing to Address 0 by reg- ister write will not put the Phy in the MII isolate mode. Please refer to section 2.3 for additional information. PHYAD0 pin has weak internal pull-up resistor. PHYAD[4:1] pins have weak internal pull-down resistors. AN0 (LED_LINK) S, O, PU 22 This input pin controls the advertised operating mode of the DP83848H according to the following table. The value on this pin is set by connecting it to GND (0) or VCC (1) through 2.2 kΩ resis- tors. This pin should NEVER be connected directly to GND or VCC. The value set at this input is latched into the DP83848H at Hard- ware-Reset. The float/pull-down status of this pin is latched into the Basic Mode Control Register and the Auto_Negotiation Advertisement Register during Hardware-Reset. The default is 1 since this pin has an internal pull-up. LED_CFG (CRS) S, O, PU 33 LED CONFIGURATION: This strapping option determines the mode of operation of the LED pins. Default is Mode 1. Mode 1 and Mode 2 can be controlled via the strap option. All modes are con- figurable via register access. SeeTable 3 for LED Mode Selection. MDIX_EN (RX_ER) S, O, PU 34 MDIX ENABLE: Default is to enable MDIX. This strapping option disables Auto-MDIX. An external pull-down will disable Auto- MDIX mode. AN0 Advertised Mode 0 10BASE-T Half-Duplex 100BASE-TX, Half-Duplex 1 10BASE-T, Half/Full-Duplex 100BASE-TX, Half/Full-Duplex |
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