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ADUM3300ARWZ Datasheet(PDF) 8 Page - Analog Devices |
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ADUM3300ARWZ Datasheet(HTML) 8 Page - Analog Devices |
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8 / 20 page  ADuM3300/ADuM3301 Rev. 0 | Page 8 of 20 Parameter Symbol Min Typ Max Unit Test Conditions 90 Mbps (CRW Grade Only) VDD1 Supply Current IDD1 (90) 5 V/3 V Operation 41 57 mA 45 MHz logic signal freq. 3 V/5 V Operation 22 31 mA 45 MHz logic signal freq. VDD2 Supply Current IDD2 (90) 5 V/3 V Operation 15 21 mA 45 MHz logic signal freq. 3 V/5 V Operation 28 41 mA 45 MHz logic signal freq. For All Models Input Currents IIA, IIB, IIC, IID, IE1, IE2 −10 +0.01 +10 μA 0 ≤ VIA,VIB, VIC,VID ≤ VDD1 or VDD2, 0 ≤ VE1,VE2 ≤ VDD1 or VDD2 Logic High Input Threshold VIH, VEH 5 V/3 V Operation 2.0 V 3 V/5 V Operation 1.6 V Logic Low Input Threshold VIL, VEL 5 V/3 V Operation 0.8 V 3 V/5 V Operation 0.4 V VDD1, VDD2 − 0.1 VDD1, VDD2 V IOx = −20 μA, VIx = VIxH Logic High Output Voltages VOAH, VOBH, VOCH, VODH VDD1,VDD2 − 0.4 VDD1,VDD2 − 0.2 V IOx = −4 mA, VIx = VIxH 0.0 0.1 V IOx = 20 μA, VIx = VIxL 0.04 0.1 V IOx = 400 μA, VIx = VIxL Logic Low Output Voltages VOAL, VOBL, VOCL, VODL 0.2 0.4 V IOx = 4 mA, VIx = VIxL SWITCHING SPECIFICATIONS ADuM330xARW Minimum Pulse Width3 PW 1000 ns CL = 15 pF, CMOS signal levels Maximum Data Rate4 1 Mbps CL = 15 pF, CMOS signal levels Propagation Delay5 tPHL, tPLH 50 70 100 ns CL = 15 pF, CMOS signal levels Pulse-Width Distortion, |tPLH − tPHL|5 PWD 40 ns CL = 15 pF, CMOS signal levels Propagation Delay Skew6 tPSK 50 ns CL = 15 pF, CMOS signal levels Channel-to-Channel Matching7 tPSKCD/OD 50 ns CL = 15 pF, CMOS signal levels ADuM330xBRW Minimum Pulse Width3 PW 100 ns CL = 15 pF, CMOS signal levels Maximum Data Rate4 10 Mbps CL = 15 pF, CMOS signal levels Propagation Delay5 tPHL, tPLH 15 35 50 ns CL = 15 pF, CMOS signal levels Pulse-Width Distortion, |tPLH − tPHL|5 PWD 3 ns CL = 15 pF, CMOS signal levels Change vs. Temperature 5 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew6 tPSK 22 ns CL = 15 pF, CMOS signal levels Channel-to-Channel Matching, Codirectional Channels7 tPSKCD 3 ns CL = 15 pF, CMOS signal levels Channel-to-Channel Matching, Opposing-Directional Channels7 tPSKOD 6 ns CL = 15 pF, CMOS signal levels ADuM330xCRW Minimum Pulse Width3 PW 8.3 11.1 ns CL = 15 pF, CMOS signal levels Maximum Data Rate4 90 120 Mbps CL = 15 pF, CMOS signal levels Propagation Delay5 tPHL, tPLH 20 30 40 ns CL = 15 pF, CMOS signal levels Pulse-Width Distortion, |tPLH − tPHL|5 PWD 0.5 2 ns CL = 15 pF, CMOS signal levels Change vs. Temperature 3 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew6 tPSK 14 ns CL = 15 pF, CMOS signal levels Channel-to-Channel Matching, Codirectional Channels7 tPSKCD 2 ns CL = 15 pF, CMOS signal levels Channel-to-Channel Matching, Opposing-Directional Channels7 tPSKOD 5 ns CL = 15 pF, CMOS signal levels |
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