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NCP5603MNR2 Datasheet(PDF) 4 Page - ON Semiconductor |
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NCP5603MNR2 Datasheet(HTML) 4 Page - ON Semiconductor |
4 / 13 page NCP5603 http://onsemi.com 4 PIN FUNCTION DESCRIPTION Pin Symbol Type Description 1 Vout OUTPUT, PWR This pin supplies the regulated voltage to the external LED. Since high current transients are present in this pin, care must be observed to avoid voltage spikes in the system. Good high frequency layout technique must be observed. 2 C1N POWER One side of the external charge pump capacitor (CFLY) is connected to this pin, associated with C1P, pin 9. Using low ESR ceramic capacitor is recommended to optimize the Charge Pump efficiency. 3 Vbat POWER This pin shall be connected to the power source, and must be decoupled to Ground by a low ESR capacitor (2.2 mF/6.3 V ceramic or better (see Note 1)). 4 Fsel INPUT, Digital This pin is used to program the operating frequency: Fsel = 0 → Fop = 262 kHz Fsel = 1 → Fop = 650 kHz 5 Vsel INPUT, Digital This pin setup the output voltage: Vsel = 0 → Vout = 4.5 V Vsel = 1 → Vout = 5.0 V 6 EN/PWM INPUT, Digital This pin controls the activity of the NCP5603 chip: EN/PWM = Low → the chip is deactivated, the load is disconnected EN/PWM = High → the chip is activated and the load is connected to the regulated output current. The NCP5603 can operate either in a continuous mode (EN/PWM = High), or can be controlled by a PWM pulse applied to EN/PWM to dim the output light. When EN/PWM is Low, the external load is disconnected from the converter, providing a very low standby current. The pull down built−in resistance makes sure the chip is deactivated even if the EN/PWM pin is disconnected (see Note 2). 7 C2N POWER One side of the external charge pump capacitor (CFLY) is connected to this pin, associated with C2P, pin 10. Using low ESR ceramic capacitor is recommended to optimize the Charge Pump efficiency. 8 GND GROUND This pin combines the Signal ground and the Power ground and must be connected to the system ground. Using good quality ground plane is mandatory to avoid spikes on the logic signal lines. 9 C1P POWER One side of the external charge pump capacitor (CFLY) is connected to this pin, associated with C1N, pin 2. Using low ESR ceramic capacitor is recommended to optimize the Charge Pump efficiency. 10 C2P POWER One side of the external charge pump capacitor is connected to this pin, associated with C2N, pin 7. Using low ESR ceramic capacitor is recommended to optimize the Charge Pump efficiency. 1. Using ceramic 16 V working voltage capacitors is recommended to compensate the DC bias effect encountered with such type of capacitors. 2. Any external impedance connected to pin 6 shall be 10 k W or higher. |
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