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LT3462 Datasheet(PDF) 4 Page - Linear Technology |
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LT3462 Datasheet(HTML) 4 Page - Linear Technology |
4 / 8 page LT3462/LT3462A 3462af 4 OPERATIO BLOCK DIAGRA Figure 1. Block Diagram – + – + – + – + 1 3 2 ∑ VOUT VOUT D R1 (EXTERNAL) R2 (EXTERNAL) FB RAMP GENERATOR SHUTDOWN BIAS CURRENT CANCELLATION 1.2MHz* OSCILLATOR R S Q A1 E AMP A2 COMP DRIVER RC CC SW Q1 0.1 Ω GND 6 1.265V REFERENCE VIN FB 4 SDREF SDREF SDREF 3462 F02 5 *LT3462A IS 2.7MHz CS1 (EXTERNAL) CS2 (EXTERNAL) Q2 OFF → 3µA ON → 180µA ISRC SHUTDOWN CS1, CS2 OPTIONAL SOFT-START COMPONENTS DO LG The LT3462 uses a constant frequency, current mode control scheme to provide excellent line and load regula- tion. Operation can be best understood by referring to the Block Diagram in Figure 1. At the start of each oscillator cycle, the SR latch is set, turning on the power switch Q1. A voltage proportional to the switch current is added to a stabilizing ramp and the resulting sum is fed into the positive terminal of the PWM comparator. When this voltage exceeds the voltage at the output of the EAMP, the SR latch is reset, turning off the power switch. The level at the output of the EAMP is simply an amplified version of the difference between the feedback voltage and GND. In this manner, the error amplifier sets the correct peak current level to keep the output in regulation. If the error amplifier’s output increases, more current is taken from the output; if it decreases, less current is taken. One function not shown in Figure 1 is the current limit. The switch current is constantly monitored and not allowed to exceed the nominal value of 400mA. If the switch current reaches 400mA, the SR latch is reset regardless of the output state of the PWM comparator. This current limit cell protects the power switch as well as various external components connected to the LT3462. SDREF is a dual function input pin. When driven low it shuts the part down, reducing quiescent supply current to less than 10 µA. When not driven low, the SDREF pin has an internal pull-up current that turns the regulator on. Once the part is enabled, the SDREF pin sources up to 180 µA nominally at a fixed voltage of 1.265V through external resistor R2 to FB. If there is no fault condition present, FB will regulate to 0V, and VOUT will regulate to 1.265V • (–R1/R2). An optional soft-start circuit uses the fixed SDREF pull-up current and a capacitor from SDREF to VOUT to set the dV/dt on VOUT. In shutdown, an FB bias current cancellation circuit supplies up to 150 µA biasing current to external resistor R1 while VOUT is lower than FB. This function eliminates R2 loading of SDREF during shutdown. As a result, supply current in shutdown may exceed 10 µA by the amount of current flowing in R1. |
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