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NIS5112D2R2G Datasheet(PDF) 8 Page - ON Semiconductor |
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NIS5112D2R2G Datasheet(HTML) 8 Page - ON Semiconductor |
8 / 9 page NIS5112 http://onsemi.com 8 There is an inherent delay in the turn on of the electronic fuse, due to the method of gate drive used. The gate of the power FET is charged through a high impedance resistor, and from the time that the gate starts charging until the time that it reaches its threshold voltage, there will be no conduction. Once the gate reaches its threshold voltage, the output current will begin a controlled ramp up phase. This delay will be added to any timing delay due to the enable/timer circuit. Figure 8 shows a simplified diagram of the enable/timer circuit. Figure 8. Simplified Schematic Diagram of the Enable/Timer Circuit − + Enabled 2.5 V 80 mA Enable/ Timer Thermal Protection Circuit The temperature limit circuit senses the temperature of the Power FET and removes the gate drive if the maximum level is exceeded. The NIS5112 device has two different thermal limit versions, auto−retry and latch off. Auto−Retry Version The device will shut down when the thermal limit threshold is reached (TJ = 135°C, typical) and will not turn back on until the die temperature reduces down to 95 °C (40 °C hysteresis, typical). It will keep auto−retrying until the fault condition is removed or power is turned−off. Latch−Off Version For the latch−off version, the device will shut down when the thermal limit threshold is reached (TJ = 135°C, typical) and will remain off until power is reset. |
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