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AD7367ARUZ Datasheet(PDF) 5 Page - Analog Devices |
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AD7367ARUZ Datasheet(HTML) 5 Page - Analog Devices |
5 / 40 page AD7329 Rev. 0 | Page 5 of 40 B Version Parameter1 Min Typ Max Unit Test Conditions/Comments ANALOG INPUT Input Voltage Ranges Reference = 2.5 V; see Table 6 (Programmed via Range Register) ±10 V VDD = 10 V min, VSS = −10 V min, VCC = 2.7 V to 5.25 V ±5 V VDD = 5 V min, VSS = −5 V min, VCC = 2.7 V to 5.25 V ±2.5 V VDD = 5 V min, VSS = − 5 V min, VCC = 2.7 V to 5.25 V 0 to 10 V VDD = 10 V min, VSS = AGND min, VCC = 2.7 V to 5.25 V Pseudo Differential VIN− Input Range VDD = 16.5 V, VSS = −16.5 V, VCC = 5 V; see Figure 43 and Figure 44 ±3.5 V Reference = 2.5 V; range = ±10 V ±6 V Reference = 2.5 V; range = ±5 V ±5 V Reference = 2.5 V; range = ±2.5 V +3/−5 V Reference = 2.5 V; range = 0 V to +10 V DC Leakage Current ±100 nA VIN = VDD or VSS 3 nA Per channel, VIN = VDD or VSS Input Capacitance3 16 pF When in track, all ranges, single ended ADCIN± Capacitance3 7 pF When in track, ±10 V range, single ended 10 pF When in track, ±5 V range, single ended 14.5 pF When in track, ±2.5 V range, single ended 10.5 pF When in track, 0 V to +10 V range, single ended 4.0 pF When in hold, all ranges, single ended MUXOUT− Capacitance3 7.5 pF All ranges, single ended MUXOUT+ Capacitance3 13 pF All ranges, single ended REFERENCE INPUT/OUTPUT Input Voltage Range 2.5 3 V Input DC Leakage Current ±1 μA Input Capacitance 10 pF Reference Output Voltage 2.5 V Reference Output Voltage Error @ 25°C ±5 mV Reference Output Voltage TMIN to TMAX ±10 mV Reference Temperature Coefficient 25 ppm/°C 3 ppm/°C Reference Output Impedance 7 Ω LOGIC INPUTS Input High Voltage, VINH 2.4 V Input Low Voltage, VINL 0.8 V VCC = 4.75 V to 5.25 V 0.4 V VCC = 2.7 to 3.6 V Input Current, IIN ±1 μA VIN = 0 V or VDRIVE Input Capacitance, CIN3 10 pF LOGIC OUTPUTS Output High Voltage, VOH VDRIVE − 0.2 V V ISOURCE = 200 μA Output Low Voltage, VOL 0.4 V ISINK = 200 μA Floating-State Leakage Current ±1 μA Floating-State Output Capacitance3 5 pF Output Coding Straight natural binary Coding bit set to 1 in control register Twos complement Coding bit set to 0 in control register |
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