5.15

3

COMMERCIAL TEMPERATURE

72801/72811/72821/72831/72841 DUAL CMOS SyncFIFO

™

256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9

PIN DESCRIPTIONS

The 72801/72811/72821/72831/72841s two FIFOs, referred

to as FIFO A and FIFO B, are identical in every respect. The

following description defines the input and output signals for

FIFO A. The corresponding signal names for FIFO B are

provided in parentheses.

Symbol

Name I/O

Description

A Data Inputs

I

9-bit data inputs to RAM array A.

B Data Inputs

I

9-bit data inputs to RAM array B.

RSA, RSB

Reset

I

When

RSA (RSB) is set LOW, the associated internal read and write pointers of array A (B) are

set to the first location;

FFA (FFB) and PAFA (PAFB) go HIGH, and PAEA (PAEB) and EFA (EFB)

go LOW. After power-up, a reset of both FIFOs A and B is required before an initial WRITE.

WCLKA

Write Clock

I

Data is written into the FIFO A (B) on a LOW-to-HIGH transition of WCLKA (WCLKB) when the

WCLKB

write enable(s) are asserted.

WENA1

Write Enable 1

I

If FIFO A (B) is configured to have programmable flags,

WENA1 (WENB1) is the only write

WENB1

enable pin that can be used. When

WENA1 (WENB1) is LOW, data A (B) is written into the

FIFO on every LOW-to-HIGH transition WCLKA (WCLKB). If the FIFO is configured to

have two write enables,

WENA1 (WENB1) must be LOW and WENA2 (WENB2) must be HIGH

to write data into the FIFO. Data will not be written into the FIFO if

FFA (FFB) is LOW.

WENA2/

LDA

Write Enable 2/

I

FIFO A (B) is configured at reset to have either two write enables or programmable flags. If

WENB2/

LDB

Load

LDA (LDB) is HIGH at reset, this pin operates as a second write enable. If WENA2/LDA

(WENB2/

LDB) is LOW at reset this pin operates as a control to load and read the program

mable flag offsets for its respective array. If the FIFO is configured to have two write enables,

WENA1 (WENB1) must be LOW and WENA2 (WENB2) must be HIGH to write data into FIFO

A (B). Data will not be written into FIFO A (B) if

FFA (FFB) is LOW. If the FIFO is configured to

have programmable flags,

LDA(LDB) is held LOW to write or read the programmable flag

offsets.

A Data Outputs O

9-bit data outputs from RAM array A.

B Data Outputs O

9-bit data outputs from RAM array B.

RCLKA

Read Clock

I

Data is read from FIFO A (B) on a LOW-to-HIGH transition of RCLKA (RCLKB) when

RENA1

RCLKB

(

RENB1) and RENA2 (RENB2) are asserted.

RENA1

Read Enable 1

I

When

RENA1 (RENB1) and RENA2 (RENB2) are LOW, data is read from FIFO A (B) on every

RENB1

LOW-to-HIGH transition of RCLKA (RCLKB). Data will not be read from Array A (B) if

EFA

(

EFB) is LOW.

RENA2

Read Enable 2

I

When

RENA1 (RENB1) and RENA2 (RENB2) are LOW, data is read from the FIFO A (B) on

RENB2

every LOW-to-HIGH transition of RCLKA (RCLKB). Data will not be read from array A (B) if

the

EFA (EFB) is LOW.

OEA

Output Enable

I

When

OEB

EFA

Empty Flag

O

When

EFA (EFB) is LOW, FIFO A (B) is empty and further data reads from the output are

EFB

inhibited. When

EFA (EFB) is HIGH, FIFO A (B) is not empty. EFA (EFB) is synchronized to

RCLKA (RCLKB).

PAEA

Programmable

O

When

PAEA (PAEB) is LOW, FIFO A (B) is almost empty based on the offset programmed into

PAEB

Almost-Empty

the appropriate offset register. The default offset at reset is Empty+7.

PAEA (PAEB) is synchro

Flag

nized to RCLKA (RCLKB).

PAFA

Programmable

O

When

PAFA (PAFB) is LOW, FIFO A (B) is almost full based on the offset programmed into the

PAFB

Almost-Full Flag

appropriate offset register. The default offset at reset is Full-7.

PAFA (PAFB) is synchronized

to WCLKA (WCLKB).

FFA

Full Flag

O

When

FFA (FFB) is LOW, FIFO A (B) is full and further data writes into the input are inhibited.

FFB

When

FFA (FFB) is HIGH, FIFO A (B) is not full. FFA (FFB) is synchronized to WCLKA

(WCLKB).

Power

+5V power supply pin.

GND

Ground

0V ground pin.

3034 tbl 01