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IDT72201L50PF Datasheet(PDF) 8 Page - Integrated Device Technology

Part # IDT72201L50PF
Description  CMOS SyncFIFO 64 X 9, 256 x 9, 512 x 9, 1024 X 9, 2048 X 9 and 4096 x 9
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT72201L50PF Datasheet(HTML) 8 Page - Integrated Device Technology

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5.07
8
IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO
64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
OUTPUTS:
Full Flag (
FF
FF) — The Full Flag (FF) will go LOW, inhibiting
further write operation, when the device is full. If no reads are
performed after Reset (
RS), the Full Flag (FF) will go LOW
after 64 writes for the IDT72421, 256 writes for the IDT72201,
512 writes for the IDT72211, 1024 writes for the IDT72221,
2048 writes for the IDT72231, and 4096 writes for the IDT72241.
The Full Flag (
FF) is synchronized with respect to the LOW-
to-HIGH transition of the write clock (WCLK).
Empty Flag (
EF
EF) — The Empty Flag (EF) will go LOW,
inhibiting further read operations, when the read pointer is
equal to the write pointer, indicating the device is empty.
The Empty Flag (
EF) is synchronized with respect to the
LOW-to-HIGH transition of the read clock (RCLK).
Programmable Almost-Full Flag (
PAF
PAF) — The
Programmable Almost-Full Flag (
PAF) will go LOW when the
FIFO reaches the Almost-Full condition. If no reads are
performed after Reset (
RS), the Programmable Almost-Full
Flag (
PAF) will go LOW after (64-m) writes for the IDT72421,
(256-m) writes for the IDT72201, (512-m) writes for the
IDT72211, (1024-m) writes for the IDT72221, (2048-m) writes
for the IDT72231, and (4096-m) writes for the IDT72241. The
offset “m” is defined in the Full offset registers.
If there is no Full offset specified, the Programmable
Almost-Full Flag (
PAF) will go LOW at Full-7 words.
The Programmable Almost-Full Flag (
PAF) is synchronized
with respect to the LOW-to-HIGH transition of the write clock
(WCLK).
Programmable Almost-Empty Flag (
PAE
PAE) — The
Programmable Almost-Empty Flag (
PAE) will go LOW when
the read pointer is "n+1" locations less than the write pointer.
The offset "n" is defined in the Empty offset registers. If no
reads are performed after Reset the Programmable Almost-
Empty Flag (
PAE) will go HIGH after "n+1" for the IDT72421/
72201/72211/72221/72231/72241.
If there is no Empty offset specified, the Programmable
Almost-Empty Flag (
PAE) will go LOW at Empty+7 words.
The Programmable Almost-Empty Flag (
PAE) is
synchronized with respect to the LOW-to-HIGH transition of
the read clock (RCLK).
Data Outputs (Q0 - Q8) — Data outputs for a 9-bit wide
data.
TABLE 1: STATUS FLAGS
NUMBER OF WORDS IN FIFO
72421
72201
72211
FF
FF
PAF
PAF
PAE
PAE
EF
EF
00
0
H
H
L
L
1 to n
1 to n
1 to n
H
H
L
H
(n+1) to (64-(m+1))
(n+1) to (256-(m+1))
(n+1) to (512-(m+1))
HHHH
(64-m)
to 63
(256-m)
to 255
(512-m)
to 511
H
L
H
H
64
256
512
L
L
H
H
(1)
(1)
NUMBER OF WORDS IN FIFO
72221
72231
72241
FF
FF
PAF
PAF
PAE
PAE
EF
EF
00
0
H
H
L
L
1 to n
(1)
1 to n
(1)
1 to n
(1)
HH
L
H
(n+1) to (1024-(m+1))
(n+1) to (2048-(m+1))
(n+1) to (4096-(m+1))
HHHH
(1024-m)
(2) to 1023
(2048-m)
(2) to 2047
(4096-m)
(2) to 4095
H
L
H
H
1024
2048
4096
L
L
H
H
NOTES:
1. n = Empty Offset (n = 7 default value)
2. m = Full Offset (m = 7 default value)
(1)
(2)
(2)
(2)
2655 tbl 10
2655 tbl 11


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