PCK9448 datasheet(7/20 Pages) PHILIPS

Part #	PCK9448

Description	3.3 V/2.5 V LVCMOS 1 : 12 clock fan-out buffer

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Manufacturer	PHILIPS [NXP Semiconductors]

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9397 750 12534

Product data sheet

Rev. 01 — 29 November 2005

7 of 20

Philips Semiconductors

PCK9448

3.3 V/2.5 V LVCMOS 1 : 12 clock fan-out buffer

[1]

Dynamic characteristics apply for parallel output termination of 50

Ω to V

T.

[2]

VICR (AC) is the cross-point of the differential input signal. Normal AC operation is obtained when the cross-point is within the VICR range

and the input swing lies within the Vi(p-p) (AC) speciﬁcation. Violation of VICR or Vi(p-p) impacts static phase offset.

[3]

See Section 9 “Application information” for part-to-part skew calculation.

[4]

Setup and hold times are referenced to the falling edge of the selected clock signal input.

Table 9:

Dynamic characteristics (2.5 V)

Tamb = −40 °C to +85 °C; VCC = 2.5 V ± 5 %; unless otherwise speciﬁed. [1]

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Vi(p-p)

input voltage (peak-to-peak value)

(PCLK, PCLK)

LVPECL

400

-

1000

mV

VICR [2]

common-mode input voltage range

(PCLK, PCLK)

LVPECL

1.2

VCC − 0.8 V

fi

input frequency

0

-

350

MHz

fo

output frequency

0

-

350

MHz

tsk(o)

output skew time

output-to-output

[3] -

-

150

ps

tsk(pr)

process skew time

part-to-part; PCLK or

CCLK to any Q

-

2.7

ns

δo

output duty cycle

δ

ref = 50 %

45

50

60

%

tPLH

LOW-to-HIGH propagation delay

PCLK to any Q

1.5

-

4.2

ns

CCLK to any Q

1.7

-

4.4

ns

tPHL

HIGH-to-LOW propagation delay

PCLK to any Q

1.5

-

4.2

ns

CCLK to any Q

1.7

-

4.4

ns

tPLZ

LOW to OFF-state propagation delay

OE to any Q

-

11

ns

tPHZ

HIGH to OFF-state propagation delay

OE to any Q

-

11

ns

tPZL

OFF-state to LOW propagation delay

OE to any Q

-

11

ns

tPZH

OFF-state to HIGH propagation delay

OE to any Q

-

11

ns

tsu

setup time

CCLK to CLK_STOP

[4] 0.0

-

ns

PCLK to CLK_STOP

[4] 0.0

-

ns

th

hold time

CCLK to CLK_STOP

[4] 1.0

-

ns

PCLK to CLK_STOP

[4] 1.5

-

ns

tr

rise time

input CCLK; 0.8 V to 2.0 V

-

1.0

ns

output; 0.6 V to 1.8 V

0.1

-

1.0

ns

tf

fall time

input CCLK; 2.0 V to 0.8 V

-

1.0

ns

output; 1.8 V to 0.6 V

0.1

-

1.0

ns

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