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AD8317 Datasheet(PDF) 11 Page - Analog Devices |
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AD8317 Datasheet(HTML) 11 Page - Analog Devices |
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11 / 20 page  AD8317 Rev. 0 | Page 11 of 20 THEORY OF OPERATION The AD8317 is a 6-stage demodulating logarithmic amplifier, specifically designed for use in RF measurement and power control applications at frequencies up to 10 GHz. A block diagram is shown in Figure 21. Sharing much of its design with the AD8318 logarithmic detector/controller, the AD8317 maintains tight inter- cept variability vs. temperature over a 50 dB range. Additional enhancements over the AD8318, such as reduced RF burst response time of 8 ns to 10 ns, 22 mA supply current, and board space requirements of only 2 mm x 3 mm, add to the low cost and high performance benefits found in the AD8317. GAIN BIAS SLOPE DET DET DET DET INHI INLO IV VOUT VSET CLPF TADJ VPOS COMM IV Figure 21. Block Diagram A fully differential design, using a proprietary, high speed SiGe process, extends high frequency performance. Input INHI receives the signal with a low frequency impedance of nominally 500 Ω in parallel with 0.7 pF. The maximum input with ±1 dB log- conformance error is typically 0 dBm (re: 50 Ω). The noise spectral density referred to the input is 1.15 nV/√Hz, which is equivalent to a voltage of 118 μV rms in a 10.5 GHz bandwidth or a noise power of −66 dBm (re: 50 Ω). This noise spectral density sets the lower limit of the dynamic range. However, the low end accuracy of the AD8317 is enhanced by specially shaping the demodulating transfer characteristic to partially compensate for errors due to internal noise. The common pin, COMM, provides a quality low impedance connection to the printed circuit board (PCB) ground. The package paddle, which is internally connected to the COMM pin, should also be grounded to the PCB to reduce thermal impedance from the die to the PCB. The logarithmic function is approximated in a piecewise fashion by six cascaded gain stages. (For a more comprehensive explanation of the logarithm approximation, please refer to the AD8307 data sheet, available at www.analog.com.) The cells have a nominal voltage gain of 9 dB each and a 3 dB bandwidth of 10.5 GHz. Using precision biasing, the gain is stabilized over temperature and supply variations. The overall dc gain is high, due to the cascaded nature of the gain stages. An offset compensation loop is included to correct for offsets within the cascaded cells. At the output of each of the gain stages, a square- law detector cell is used to rectify the signal. The RF signal voltages are converted to a fluctuating differential current having an average value that increases with signal level. Along with the six gain stages and detector cells, an additional detector is included at the input of the AD8317, providing a 50 dB dynamic range in total. After the detector currents are summed and filtered, the following function is formed at the summing node: ID × log10(VIN/VINTERCEPT) where: ID is the internally set detector current. VIN is the input signal voltage. VINTERCEPT is the intercept voltage (that is, when VIN = VINTERCEPT, the output voltage would be 0 V, if it were capable of going to 0 V). |
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