AD8382ACP datasheet(3/24 Pages) AD

Part #	AD8382ACP

Description	High Performance 12-Bit, 6-Channel Output, Decimating LCD DecDriver

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Manufacturer	AD [Analog Devices]

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AD8382

Rev. 0 | Page 3 of 24

SPECIFICATIONS

Table 1. @ 25°C, AVCC = 15.5 V, DVCC = 3.3 V, TMIN = 0°C, TMAX = 85°C, VREFHI = 9.5 V, VREFLO = V1 = V2 = 7 V, unless

otherwise noted.

Parameter

Conditions

Min

Typ

Max

Unit

VIDEO DC PERFORMANCE1

TMIN to TMAX

VDE

DAC Code 1500 to 3200

–5

+5

mV

VCME

DAC Code 1500 to 3200

–3.5

+0.5

+3.5

mV

∆V

DAC Code 2048

2.5

7.5

mV

∆V

DAC Code 0 to 4095

4

15

mV

VIDEO OUTPUT DYNAMIC PERFORMANCE

TC, MIN to TC, MAX,

VO = 5 V Step, CL = 200 pF

Data Switching Slew Rate

20% to 80%

390

V/

µs

Invert Switching Slew Rate

20% to 80%

530

V/

µs

Data Switching Settling Time to 1%

22

27

ns

Data Switching Settling Time to 0.25%

33

50

ns

Invert Switching Settling Time to 1%

34

100

ns

Invert Switching Settling Time to 0.25%

130

300

ns

Invert Switch Overshoot

100

200

mV

CLK and Data Feedthrough2

10

mV p-p

All-Hostile Crosstalk3

Amplitude

40

mV p-p

Duration

30

ns

DAC Transition Glitch Energy

Code 2047 to Code 2048

0.3

nV-s

VIDEO OUTPUT CHARACTERISTICS

Output Voltage Swing

AVCC – VOH, VOL– AGND

1.1

1.3

V

CLK to VID Delay: t94

50% of VIDx

10

12

14

ns

INV to VID Delay: t10

50% of VIDx

10.4

12.4

14.4

ns

Output Current

100

mA

Output Resistance

22

Ω

RESOLUTION

Coding

Binary

12

Bits

DIGITAL INPUT CHARACTERISTICS

Input tr, tf = 2 ns (10% to 90%)

Max. Input Data Update Rate

120

Ms/s

Data Setup Time: t1

0

ns

STSQ Setup Time: t3

1

ns

XFR Setup Time: t5

1

ns

Data Hold Time: t2

3

ns

STSQ Hold Time: t4

3

ns

XFR Hold Time: t6

3

ns

CLK High Time: t7

3

ns

CLK Low Time: t8

2.5

ns

CIN

3

pF

IIH

0.05

µA

IIL—All Inputs except CLK

0.6

µA

IIL—CLK

1.2

µA

VIH

2

V

VIL

0.8

V

VTH

1.6

V

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