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AD9704BCPZRL7 Datasheet(PDF) 11 Page - Analog Devices

Part # AD9704BCPZRL7
Description  8-/10-/12-/14-Bit, 175 MSPS TxDAC D/A Converters
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9704BCPZRL7 Datasheet(HTML) 11 Page - Analog Devices

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AD9704/AD9705/AD9706/AD9707
Rev. 0 | Page 11 of 52
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
AD9707
AD9707
TOP VIEW
(Not to Scale)
PIN 1
INDICATOR
8
7
6
5
4
3
2
1
DB1
DB2
DB3
DB4
DB5
DVDD
DB6
DB7
17
18
19
20
21
22
23
24
PIN/SPI/RESET
AVDD
OTCM
IOUTB
IOUTA
ACOM
REFIO
FS ADJ
Figure 3. AD9707 Pin Configuration
Table 9. AD9707 Pin Function Descriptions
Pin No.
Mnemonic
Description
27
DB13 (MSB)
Most Significant Data Bit (MSB).
28 to 32,
1, 2, 4 to 8
DB12 to DB1
Data Bit 12 to Data Bit 1.
9
DB0 (LSB)
Least Significant Data Bit (LSB).
25
SLEEP/CSB
In pin mode, active high powers down chip.
In SPI mode, this pin is the serial port chip select (active low).
23
REFIO
Reference Input/Output. Serves as reference input when internal reference disabled. Serves as 1.0 V reference
output when internal reference activated. Requires a 0.1 μF capacitor to ACOM when internal reference activated.
24
FS ADJ
Full-Scale Current Output Adjust.
22
ACOM
Analog Common.
20
IOUTB
Complementary DAC Current Output. Full-scale current is sourced when all data bits are 0s.
21
IOUTA
DAC Current Output. Full-scale current is sourced when all data bits are 1s.
18
AVDD
Analog Supply Voltage (1.7 V to 3.6 V).
19
OTCM
Adjustable Output Common Mode. Refer to the Theory of Operation section for details.
17
PIN/SPI/RESET
Selects SPI mode or pin mode operation. Active high for pin mode operation. Active low for SPI mode
operation. Pulse high to reset SPI registers to default values.
16
MODE/SDIO
In pin mode, this selects the input data format. Connect to DCOM for straight binary, DVDD for twos complement.
In SPI mode, this pin acts as SPI data input/output.
15
CMODE/SCLK
In pin mode, this pin selects the clock input type. Connect to CLKCOM for single-ended clock receiver
(drive CLK+ and float CLK–). Connect to CLKVDD for differential receiver.
In SPI mode, this pin is the serial data clock input.
14
CLKCOM
Clock Common.
13
CLK−
Differential Clock Input.
12
CLK+
Differential Clock Input.
11
CLKVDD
Clock Supply Voltage (1.7 V to 3.6 V).
10, 26
DCOM
Digital Common.
3
DVDD
Digital Supply Voltage (1.7 V to 3.6 V).


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