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AD73411 Datasheet(PDF) 4 Page - Analog Devices

Part No. AD73411
Description  Low-Power Analog Front End with DSP Microcomputer
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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REV. 0
–4–
AD73411–SPECIFICATIONS
Parameter
Test Conditions
Min
Typ
Max
Unit
DSP SECTION
VIH
Hi-Level Input Voltage
1, 2
@ VDD = max
2.0
V
VIH
Hi-Level CLKIN Voltage
@ VDD = max
2.2
V
VIL
Lo-Level Input Voltage
1, 3
@ VDD = min
0.8
V
VOH
Hi-Level Output Voltage
1, 4, 5
@ VDD = min
IOH = –0.5 mA
2.4
V
@ VDD = min
IOH = –100
µA6
VDD – 0.3
V
VOL
Lo-Level Output Voltage
1, 4, 5
@ VDD = min
IOL = 2 mA
0.4
V
IIH
Hi-Level Input Current
3
@ VDD = max
VIN = VDD max
10
µA
IIL
Lo-Level Input Current
3
@ VDD = max
VIN = 0 V
10
µA
IOZH
Three-State Leakage Current
7
@ VDD = max
VIN = VDD max
8
10
µA
IOZL
Three-State Leakage Current
7
@ VDD = max
VIN = 0 V
8
10
µA
IDD
Supply Current (Idle)
9
@ VDD = 3.3
tCK = 19 ns
10
12
mA
tCK = 25 ns
10
11
mA
tCK = 30 ns
10
10
mA
IDD
Supply Current (Dynamic)
11
@ VDD = 3.3
TAMB = 25
°C
tCK = 19 ns
10
45
mA
tCK = 25 ns
10
43
mA
tCK = 30 ns
10
36
mA
CI
Input Pin Capacitance
3, 6, 12
@ VIN = 2.5 V
fIN = 1.0 MHz
TAMB = 25
°C8
pF
CO
Output Pin Capacitance
6, 7, 12, 13
@ VIN = 2.5 V
fIN = 1.0 MHz
TAMB = 25
°C8
pF
NOTES
1 Bidirectional pins: D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1–A13, PF0–PF7.
2 Input only pins:
RESET, BR, DR0, DR1, PWD.
3 Input only pins: CLKIN,
RESET, BR, DR0, DR1, PWD.
4 Output pins:
BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2–0, BGH.
5 Although specified for TTL outputs, all AD73411 outputs are CMOS-compatible and will drive to VDD and GND, assuming no dc loads.
6 Guaranteed but not tested.
7 Three-statable pins: A0–A13, D0–D23,
PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF0–PF7.
8 0 V on
BR.
9 Idle refers to AD73411 state of operation during execution of IDLE instruction. Deasserted pins are driven to either VDD or GND.
10 V
IN = 0 V and 3 V. For typical figures for supply currents, refer to Power Dissipation section.
11 I
DD measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (Types 1, 4, 5, 12, 13, 14), 30% are Type 2
and Type 6, and 20% are idle instructions.
12 Applies to PBGA package type.
13 Output pin capacitance is the capacitive load for any three-stated output pin.
Specifications subject to change without notice.
(AVDD = DVDD = VDD = 3.0 V to 3.6 V; DGND = AGND = 0 V, fMCLK = 16.384 MHz,
fSAMP = 64 kHz; TA = TMIN to TMAX, unless otherwise noted.)




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