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AD96606 Datasheet(PDF) 8 Page - Analog Devices |
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AD96606 Datasheet(HTML) 8 Page - Analog Devices |
8 / 12 page REV. 0 –8– AD9660 Initial calibration is required after power-up or any other time the laser has been disabled. Disabling the AD9660 drives the hold capacitors back down to VREF. In this case, or in any case where the output current is more than 10% out of calibration, R will range from 300 Ω to 550 Ω for the model above; the higher value should be used for calculating the worst case calibration time. Following the example above, if CHOLD were chosen as 4.5 nF, then τ = RC = 550 Ω × 4.5 nF would be 2.5 µs. For an initial calibration error <1%, the initial calibration time should be >5 τ = 12.4 µs. Initial calibration time will actually be better than this calcula- tion indicates, as a significant portion of the calibration time will be within 10% of the final value, and the output resistance in the AD9660’s T/H decreases as the hold voltage approaches its final value. Recalibration is functionally identical to initial calibration, but the loop need only correct for droop. Because droop is assumed to be a small percentage of the initial calibration (<10%), the resistance for the model above will be in the range of 75 Ω to 140 Ω. Again, the higher value should be used to estimate the worst case time needed for recalibration. Continuing with the example above, since the error during hold time was chosen as 5%, we meet the criteria for recalibration and τ = RC = 140 Ω × 4.5 nF = 0.63 µs. To get a final error of 1% after recalibration, the 5% droop must be corrected to within a 20% error (20% × 5% = 1%). A 2τ recalibration time of 1.26 µs is sufficient. Continuous Recalibration In applications where the hold capacitor is small (<500 pF) and the WRITE PULSE signals always have a pulse width >25 ns, the user may continuously calibrate the write loop. In such an application, the WRITE CAL signal should be held logic HIGH, and the WRITE PULSE signal will control write loop calibration via the internal AND gate. The bias loop may be continuously recalibrated whenever WRITE PULSE is logic LOW. Using this model, the voltage at the hold capacitor is VC HOLD = V t = 0 + (Vt =∞ − Vt = 0)1 − e −t τ where t0 is when the calibration begins (WRITE CAL or BIAS CAL goes logic HIGH), Vt = 0 is the voltage on the hold cap at t = 0, Vt = ∞ is the steady state voltage at the hold cap with the loop closed, and τ = R CHOLD is the time constant. With this model the error in VC HOLD for a finite calibration time, as com- pared to Vt = ∞, can be estimated from the following table and chart: Table II. tCALIBRATION % Final Value Error % 7 τ 99.9 0.09 6 τ 99.7 0.25 5 τ 99.2 0.79 4 τ 98.1 1.83 3 τ 95.0 4.97 2 τ 86.5 13.5 τ 63.2 36.8 CALIBRATION TIME – Time Constants = 100 30 0 05 1 24 20 10 3 40 50 60 70 80 90 Figure 8. Calibration Time Curve |
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