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MAX5079EUD Datasheet(PDF) 11 Page - Maxim Integrated Products |
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MAX5079EUD Datasheet(HTML) 11 Page - Maxim Integrated Products |
11 / 18 page ORing MOSFET Controller with Ultra-Fast 200ns Turn-Off ______________________________________________________________________________________ 11 c. During the hot insertion, a voltage spike can occur at N1 and N2 and cause the (VOUT1 to VBUS) or (VOUT2 to VBUS) voltage to go negative. If the reverse voltage is below the fast-comparator reverse voltage threshold (VFTH) but above the programmed slow-comparator reverse voltage threshold (VSTH), the spike is ignored for the pro- grammed blanking time (tSTH). If the spike is longer than 50ns (the fast-comparator internal blanking time, tFBL) and larger than VFTH, then U1 and U2 will turn off N1 and N2 quickly. If the mag- nitude of the voltage spike is above VSTH but less than VFTH, and longer than the slow-comparator blanking time (tSTH), U1 and U2 will turn off their respective ORing MOSFETs (N1 and N2) by dis- charging their GATE pins to PGND. The external load-sharing circuit of PS1 and PS2 will force VOUT1, VOUT2 above VBUS and N1, N2 will turn back on through the 2mA current sourcing from the GATE pins of U1 and U2. To avoid this situa- tion the user can set the slow-comparator thresh- old and blanking time depending on the magnitude and duration of the voltage spikes. d. PS3 fails to start. VUVLO (U3) threshold is not crossed and U3 keeps N3 off. e. PS3 goes into an overvoltage condition (no feed- back). This causes VBUS to go into an overvoltage condition increasing the loading on PS3 (provided PS3 is able to supply all the required BUS cur- rent). The current-sharing circuit will force the out- puts of PS1 and PS2 to increase and eventually saturate at their current-sharing voltage range. Eventually only PS3 will have a positive voltage at IN (U3) with respect to BUS. PS1 and PS2 will have a negative voltage at VOUT1 and VOUT2 with respect to BUS. All overvoltage inputs OVI (U1), OVI (U2), and OVI (U3) sense the overvoltage, but only OVP (U3) is asserted and latched low. GATE (U3) is pulled to PGND and remains low as long as VOVI ≥ 0.6V. When VOVI drops below 0.6V, OVP remains low. However, U3 tries to turn on N3 unless VOUT3 is actively kept below the undervolt- age lockout. Use OVP (U3) to either drive the cathode of the optocoupler to shutdown PS3 from the primary side or use OVP (U3) to fire an SCR connected between VOUT3 and PGND. 3) PS1, PS2, PS3 are turned on with a shorted BUS. Body diodes of N1, N2, and N3 conduct and short the outputs of PS1, PS2, and PS3 to PGND. The power supplies go into current limit (either in foldback or in hiccup mode). The MAX5079s remain in undervoltage lockout and keep all ORing MOSFETs off. The average current sourced by PS1, PS2, or PS3 must be low enough so as not to exceed the MOSFETs power dissi- pation (PD = VF x ISHORT). a. Use additional n-channel MOSFETs in series with N1, N2, and N3 in the reverse direction to isolate the power supplies from a shorted bus (Figure 3). When power is turned on with a shorted bus, VIN_ (U1, U2, U3) increases and VUVLO rises above the UVLO threshold. The MAX5079’s GATE out- puts start charging the back-to-back ORing MOSFET gates. The short-circuit condition at BUS collapses VIN (U1), VIN (U2), and VIN (U3) send- ing the MAX5079s into undervoltage lockout. This turns off the MAX5079s entirely, including dis- charging of the charge-pump storage capacitors. The IN voltages come back up again crossing UVLO (UVLO has 60mV hysteresis). A new cycle starts and the time required to charge the charge- pump capacitor and the turn-on time of the device serves as a dead time. However, the dead time may not be enough to reduce the dissipation in the MOSFETs to an acceptable level. We advise in keeping the short-circuit current low and pro- viding hiccup current-limit protection to the power supplies (PS1, PS2, and PS3). b. Any other overload condition that would sustain the IN voltage above UVLO, will keep the MOSFETs ON continuously. Ensure the MOSFETs’ current rating is higher than the maximum short-circuit source current of the power supplies (PS1, PS2, and PS3) to avoid damage to the ORing MOSFETs. 4) PS1, PS2, and PS3 are present and PS1 is short- ed to GND. VOUT1 drops below VBUS. The negative potential from VIN (U1) to VBUS increases above the fast-comparator threshold and lasts longer than the 50ns blanking time. The MAX5079 (U1) takes its power from the voltage at BUS (U1). Connect BUS close to CBUS, away from N1 so that U1 can receive power from BUS for a few microseconds until N1 isolates BUS from IN. N1 is dis- charged with 2A pulldown current, turning off N1 and isolating PS1 from the BUS. The load-sharing circuit of PS2 and PS3 will increase PS2 and PS3’s load current until the total bus current requirement is satisfied. For VIN (U1) < 2.75V, VAUXIN (U1) must come from an independent source or remain on for some time (a few microseconds) after VIN (U1) has failed. This minimum on-time is needed to discharge the gate of the ORing MOSFET and isolate PS1 from the BUS. |
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