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AM42DL6404G70IT Datasheet(PDF) 11 Page - SPANSION |
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AM42DL6404G70IT Datasheet(HTML) 11 Page - SPANSION |
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11 / 61 page  10 Am42DL6404G March 20, 2002 PR ELI M I NARY MCP DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory loca- tion. The register is a latch used to store the com- mands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Tables 1-2 lists the device bus operations, the inputs and control levels they require, and the result- ing output. The following subsections describe each of these operations in further detail. Table 1. Device Bus Operations—Flash Word Mode, CIOf = VIH Legend: L = Logic Low = V IL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SADD = Flash Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out Notes: 1. Other operations except for those indicated in this column are inhibited. 2. Do not apply CE#f = V IL, CE1#s = VIL and CE2s = VIH at the same time. 3. Don’t care or open LB#s or UB#s. 4. If WP#/ACC = VIL, the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed. If WP#/ACC = V ACC (9V), the program time will be reduced by 40%. 5. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector Block Protection and Unprotection” section. 6. If WP#/ACC = V IL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. If WP#/ACC = V HH, all sectors will be unprotected. Operation (Notes 1, 2) CE#f CE1#s CE2s OE# WE# Addr. LB#s UB#s RESET# WP#/ACC (Note 4) DQ7– DQ0 DQ15– DQ8 Read from Flash L HX LH A IN XX H L/H D OUT D OUT XL Write to Flash L HX HL A IN X X H (Note 4) D IN D IN XL Standby V CC ± 0.3 V HX XX X X X V CC ± 0.3 V H High-Z High-Z XL Output Disable L L H HH X L X H L/H High-Z High-Z HH X X L Flash Hardware Reset X HX X X X X X L L/H High-Z High-Z XL Sector Protect (Note 5) L HX HL SADD, A6 = L, A1 = H, A0 = L XX V ID L/H D IN X XL Sector Unprotect (Note 5) L HX HL SADD, A6 = H, A1 = H, A0 = L XX V ID (Note 6) D IN X XL Temporary Sector Unprotect X HX XX X X X V ID (Note 6) D IN High-Z XL Read from SRAM H L H L H A IN LL HX D OUT D OUT HL High-Z D OUT LH DOUT High-Z Write to SRAM H L H X L A IN LL HX D IN D IN HL High-Z D IN LH D IN High-Z |
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