4

Pin Description

SYMBOL

PLCC PIN

NUMBER

TYPE

DESCRIPTION

1, 68

recommended.

GND

2, 3

GND. The device ground.

X0-X15

47-59, 61-63

I

X-Input Data. These 16 data inputs provide the multiplicand which may be in two's complement

or unsigned magnitude format.

Y0-Y15/

P0-P15

27-42

I/O

Y-Input/LSP Output Data. This 16-bit port is used to provide the multiplier which may be in two's

complement or unsigned magnitude format. It may also be used for output of the Least Significant

Product (LSP).

P16-P31/

P0-P15

10-25

O

Output Data. This 16-bit port may provide either the MSP (P16-31) or the LSP (P0-15).

TCY, TCX

66, 67

I

Two's Complement Control. Input data is interpreted as two's complement when this control is

HIGH. A LOW indicates the data is to be interpreted as unsigned magnitude format.

FT

5

I

Feed through Control. When this control is HIGH, both the MSP and LSP Registers are

transparent. When LOW, the registers are latched by their associated clock signals.

FA

6

I

Format Adjust Control. A full 32-bit product is selected when this control line is HIGH. A LOW on

this control line selects a left shifted 31-bit product with the sign bit replicated in the LSP. This

control is normally HIGH, except for certain two's complement integer and fractional

applications.

RND

65

I

Round Control. When this control is HIGH, a one is added to the Most Significant Bit (MSB) of the

LSP. This position is dependent on the FA control; FA = HIGH indicates RND adds to the 2-15 bit

MSPSEL

4

I

Output Multiplexer Control. When this control is LOW, the MSP is available for output at the

dedicated output port, and the LSP is available at the Y-input/LSP output port. When MSPSEL is

HIGH, the LSP is available at both ports and the MSP is not available for output.

OEL

46

I

Y-In/P0-15 Output Port Three-State Control. When OEL is HIGH, the output drivers are in the high

impedance state. This state is required for Ydata input. When OEL is LOW, the port is enabled for

LSP output.

OEP

7

I

P16-31/P0-15 Output Port Three-State Control. A LOW on this control line enables the output

port. When OEP is HIGH, the output drivers are in the high impedance state.

THE FOLLOWING PIN DESCRIPTIONS APPLY TO THE HMU16 ONLY

CLKX

64

I

X-Register Clock. The rising edge of this clock loads the X-data Input Register along with the TCX

and RND Registers.

CLKY

44

I

Y-Register Clock. The rising edge of this clock loads the Y-data Input Register along with the TCY

and RND Registers.

CLKM

8

I

MSP Register Clock. The rising edge of CLKM loads the Most Significant Product (MSP) Register.

CLKL

45

I

LSP Register Clock. The rising edge of CLKL loads the Least Significant Product (LSP) Register.

THE FOLLOWING PIN DESCRIPTIONS APPLY TO THE HMU17 ONLY

CLK

45

I

Clock. The rising edge of this clock will load all enabled registers.

ENX

64

I

X-Register Enable. When ENX is LOW, the X-register is enabled; X-input data and TCX will be

latched at the rising edge of CLK. When ENX is high, the X-register is in a hold mode.

ENY

44

I

Y-Register Enable. ENY enables the Y-register. (See ENX).

ENP

8

I

Product Register Enable. ENP enables the Product Register. Both the MSP and LSP

Sections are enabled by ENP.(See ENX).

HMU16, HMU17