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TPS73033DBVR Datasheet(PDF) 8 Page - Texas Instruments |
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TPS73033DBVR Datasheet(HTML) 8 Page - Texas Instruments |
8 / 16 page www.ti.com Power Dissipation and Junction Temperature P D(max) + T J max *TA R Q JA (1) P D + VIN*VOUT I OUT (2) Programming the TPS73001 Adjustable LDO Regulator V OUT + VREF 1 ) R 1 R 2 (3) R = 1 - 1 ´ R2 V OUT V REF (4) C 1 + (3 x 10*7) x (R 1 ) R2) (R 1 x R2) (5) TPS730xx SBVS054G – NOVEMBER 2004 – REVISED DECEMBER 2006 APPLICATION INFORMATION (continued) Specified regulator operation is assured to a junction temperature of +125 °C; the maximum junction temperature should be restricted to +125 °C under normal operating conditions. This restriction limits the power dissipation the regulator can handle in any given application. To ensure the junction temperature is within acceptable limits, calculate the maximum allowable dissipation, PD(max), and the actual dissipation, PD, which must be less than or equal to PD(max). The maximum power dissipation limit is determined using Equation 1: Where: • T Jmax is the maximum allowable junction temperature. • Rθ JA is the thermal resistance junction-to-ambient for the package (see the Dissipation Ratings Table). • T A is the ambient temperature. The regulator dissipation is calculated using Equation 2: Power dissipation resulting from quiescent current is negligible. Excessive power dissipation triggers the thermal protection circuit. The output voltage of the TPS73001 adjustable regulator is programmed using an external resistor divider as shown in Figure 17. The output voltage is calculated using Equation 3: Where: • V REF = 1.225V typ (the internal reference voltage) Resistors R1 and R2 should be chosen for approximately 50µA divider current. Lower value resistors can be used for improved noise performance, but the solution consumes more power. Higher resistor values should be avoided as leakage current into/out of FB across R1/R2 creates an offset voltage that artificially increases/decreases the feedback voltage and thus erroneously decreases/increases VOUT. The recommended design procedure is to choose R2 = 30.1kΩ to set the divider current at 50µA, C1 = 15pF for stability, and then calculate R1 using Equation 4: In order to improve the stability of the adjustable version, it is suggested that a small compensation capacitor be placed between OUT and FB. For voltages < 1.8V, the value of this capacitor should be 100pF. For voltages > 1.8V, the approximate value of this capacitor can be calculated as shown in Equation 5: The suggested value of this capacitor for several resistor ratios is shown in the table below. If this capacitor is not used (such as in a unity-gain configuration) or if an output voltage < 1.8V is chosen, then the minimum recommended output capacitor is 4.7 µF instead of 2.2µF. 8 Submit Documentation Feedback |
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