ZL30117

Data Sheet

7

Zarlink Semiconductor Inc.

Pin Description

Pin #

Name

I/O

Type

Description

Input Reference

B1

A3

B4

ref0

ref1

ref2

Input References (LVCMOS, Schmitt Trigger). These are input references

available for synchronizing output clocks. All three input references can be

automatically or manually selected using software registers. These pins are

internally pulled down to Vss.

A1

A2

A4

sync0

sync1

sync2

Frame Pulse Synchronization References (LVCMOS, Schmitt Trigger).

These are the frame pulse synchronization inputs associated with input

references 0, 1 and 2. These inputs accept frame pulses in a clock format (50%

duty cycle) or a basic frame pulse format with minimum pulse width of 5 ns.

Output Clocks and Frame Pulses

D8

sdh_clk

O

SONET/SDH Output Clock (LVCMOS). This output can be configured to

provide any one of the SONET/SDH clock outputs up to 77.76 MHz. The default

frequency for this output is 77.76 MHz.

D7

sdh_fp

O

SONET/SDH Output Frame Pulse (LVCMOS). This output can be configured to

provide virtually any style of output frame pulse synchronized with an associated

SONET/SDH family output clock. The default frequency for this frame pulse

output is 8 kHz.

G8

p_clk

O

Programmable Output Clock (LVCMOS). This output can be configured to

provide any frequency with a multiple of 8 kHz up to 77.76 MHz in addition to

2 kHz. The default frequency for this output is 2.048 MHz.

G7

p_fp

O

Programmable Output Frame Pulse (LVCMOS). This output can be configured

to provide virtually any style of output frame pulse associated with p_clk. The

default frequency for this frame pulse output is 8 kHz.

A7

B8

diff_clk_p

diff_clk_n

O

Differential Output Clock (LVPECL). This output can be configured to provide

any one of the available SDH clock frequencies. The default frequency for this

clock output is 622.08 MHz.

Control

G5

rst_b

I

Reset (LVCMOS, Schmitt Trigger). A logic low at this input resets the device. To

ensure proper operation, the device must be reset after power-up. Reset should

be asserted for a minimum of 300 ns.

B2

dpll_mod_sel

DPLL Mode Select (LVCMOS, Schmitt Trigger). During reset, the level on this

pin determines the default mode of operation of the DPLL (Normal or Freerun).

After reset, the mode of operation can be controlled directly with these pins, or by

accessing the dpll_modesel register through the serial interface. This pin is

internally pulled up to Vdd.

B3

diff_en

Differential Output Enable (LVCMOS, Schmitt Trigger). When set high, the

differential LVPECL driver is enabled. When set low, the differential driver is

tristated reducing power consumption. This function is also controllable through

software registers. This pin is internally pulled up to Vdd.