CDB5012 datasheet(4/7 Pages) CIRRUS

4 page

Reset/Self-Calibration Modes

The A/D converter will usually reset itself upon

power-up. Since this function is not guaranteed,

the converter must be reset upon power-up in

system operation. The converter can be reset on

the CDB5012, CDB5012A, CDB5014, CDB5016

board by momentarily depressing push-button

SW-2 thus initiating a full calibration cycle;

1,443,840 master clock cycles later the converter

is ready for normal operation.

The converters also feature two other calibration

modes: burst and interleave. The use of Burst

calibration is not recommended. Interleave can be

initiated by setting switch position 3 to the on

position. In the interleave mode (INTRLV low),

the converter appends one small portion of a cali-

bration cycle (20 master clock cycles) to each

conversion cycle. Thus, a full calibration cycle

completes every 72,192 conversion cycles. The

Interleave calibration mode should not be used

intermittently.

A more detailed discussion of the converters’

calibration modes and capabilities can be found

in their data sheets.

Parallel Output Data/Microprocessor Interface

The converter’s outputs D0-D15, its CS, RD, and

A0 inputs, and its EOC output are available at

the 40 pin header. The CS and RD inputs are

pulled low through 10 k

Ω resistors placing

the converter in a microprocessor-independent

mode. Control input A0 is pulled up, insuring the

converter’s output word, rather than the status

The converter’s 3-state output buffers and micro-

processor interface can be exercised by driving

the CS and/or RD inputs at the header. Similarly,

the converter’s 8-bit status register can be ob-

tained on D0-D7 by driving A0 low.

The converter’s EOC and data outputs are not

b u f f e r e d on the CDB5 01 2, CDB5 01 2A ,

CDB5014, CDB5016. Therefore, careful attention

should be paid to the load presented by any ca-

bling, especially if the 3-state output buffers are

to be exercised at speed. Twisted ribbon cable is

typically specified at 10pF/ft, so several feet can

generally be accommodated.

Serial Output Data

Serial output data is available at the two BNC

connections SCLK and SDATA. Data appears

MSB first, LSB last, and is valid on the rising

edge of SCLK.

Master Clock

The A/D converter operates from a master clock

which can either be internally-generated or exter-

nally-supplied. For operation with an external

clock, the BNC connector labeled CLKIN

should be driven with a TTL clock signal. The

CDB5012, CDB5012A, CDB5014, CDB5016 is

shipped from the factory with the CLKIN input

D10

D11

D12

D13

D14

D15

EOC

DGND

Figure 4. Header Pin Definitions

CDB5012, CDB5012A, CDB5014, CDB5016

DS14DB1

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