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CS61884-IQ Datasheet(PDF) 9 Page - Cirrus Logic

Part No. CS61884-IQ
Description  Octal T1/E1/J1 Line Interface Evaluation Board
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Maker  CIRRUS [Cirrus Logic]
Homepage  http://www.cirrus.com

 9 page
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in the open “HIGH” position selects multiplex and
the closed “LOW” position selects Non-multiplex
Digital Signal Connections
There are eight fourteen pin bed stake headers (la-
beled J4 through J11) that provide access to the
digital signals used to interface with back-end de-
vices (framers, mappers, ASIC, etc.) and all eight
LOS signals, in both hardware and host mode.
Figure 10 shows the layout for one of the eight 14-
pin bed stake headers used to access the back-end
digital signals, LOS signals and the different set-
tings for the TCLK/TNEG pins.
LOS Indicators
The two 4-LED packs D1 and D2 (labeled ALOS
0-7) represent the LOS signal status for LOS 0-7
pins. The ALOS 0-7 LEDs will illuminate when the
corresponding receiver has detected a loss of signal
condition. Refer to the CS61884 Data Sheet for
LOS conditions.
JTAG Connection
A 5-pin bed stake header (J60) is provided to allow
easy access to the IEEE 1149.1 JTAG Boundary
Scan signals from the device.
Host Interface Connection
Connector J12 is used to connect the CS61884
evaluation board to the host computer, through a
standard 25 pin male to female parallel port cable.
No external
µController board is required for host
interface connection. This connector is used for
both serial and parallel interface.
Place the switches shown in Table 3 to the stated
configuration before setting the Mode switch (S15)
to Serial or Parallel host mode. Refer to the
Figure 4 on page 6 for switch S15 settings.
– Switches #1 and #2 inside of switch block S9
are used in parallel host mode to select
Motorola, Intel, multiplex or Non-multiplex
modes. Switch S9 #1 and #2 are not used in
Serial host mode.
The software provided with the CDB61884 evalu-
ation board is used to control and monitor the
CS61884 device. The program is designed to auto-
matically read back each bit after each write. If the
bit is read back incorrectly an error will occur. The
Bi-polar Mode
TAOS active when
MCLK present
RZ mode active when
MCLK absent
Transmitters High-Z
Uni-Polar Mode Active
Figure 10. Digital Signal Control/Access
Table 3. Switch Settings for Host Mode
S1 through S8
NONE (middle)
S9 # 3 through # 7
OPEN (low)
OPEN (middle)
NC (middle)
S12 through S14
OPEN (middle)

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