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CS3308 Datasheet(PDF) 11 Page - Cirrus Logic |
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CS3308 Datasheet(HTML) 11 Page - Cirrus Logic |
11 / 44 page DS702F1 11 CS3308 CONTROL PORT SWITCHING CHARACTERISTICS - SPI™ FORMAT (Inputs: Logic 0 = DGND, Logic 1 = VD, CL =20pF) 8. Data must be held for sufficient time to bridge the transition time of CCLK. 9. For fsck <1 MHz. Parameter Symbol Min Max Unit CCLK Clock Frequency fsck 06.0 MHz RESET Rising Edge to CS Falling tsrs 100 - ns CS High Time Between Transmissions tcsh 1.0 - μs CS Falling to CCLK Edge tcss 20 - ns CCLK Low Time tscl 66 - ns CCLK High Time tsch 66 - ns CDIN to CCLK Rising Setup Time tdsu 40 - ns CCLK Rising to DATA Hold Time (Note 8) tdh 15 - ns Rise Time of CCLK and CDIN (Note 9) tr2 - 100 ns Fall Time of CCLK and CDIN (Note 9) tf2 - 100 ns t r2 t f2 t dsu t dh t sch t scl CS MOSI t css t csh RESET t srs CCLK Figure 2. Control Port Timing - SPI Format |
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