4 / 12 page
4
Sept. 1992
AC Test Conditions
Parameter
Test Conditions
Input pulse levels
0V to 3.0V
Input rise and fall times
5 ns
Input and output timing reference levels
1.5 V (unless otherwise specified)
Output load (including scope and jig)
See Figures 1 and 2
Figure 1. Output Load A
Figure 2. Output Load B
Read Cycle (TA = 0 to 70°C, VCCmin ≤ VCC ≤ VCCmax)
Symbol
Parameter
-85
-120
Unit
Conditions
Min.
Max.
Min.
Max.
tRC
Read cycle time
85
-
120
-
ns
tAA
Address access time
-
85
-
120
ns
Output load A
tACE
Chip enable access time
-
85
-
120
ns
Output load A
tOE
Output enable to output valid
-
45
-
60
ns
Output load A
tCLZ
Chip enable to output in low Z
5
-
5
-
ns
Output load B
tOLZ
Output enable to output in low Z
0
-
0
-
ns
Output load B
tCHZ
Chip disable to output in high Z
0
35
0
45
ns
Output load B
tOHZ
Output disable to output in high Z
0
25
0
35
ns
Output load B
tOH
Output hold from address change
10
-
10
-
ns
Output load A
bq4024/bq4024Y
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
