LINEAR MAGNETIC FIELD SENSORS

9

Single Clock Circuitry—Some form of clock is needed to

trigger the set and reset pulses (Figure 6) to create the

switching signal. The circuit shown in Figure 8 can be used

to create a strong (>4Amp) pulse. The diodes, resistors,

capacitors and inverters basically create the TRS and the

TSR delays. Now a single signal (Clock) can trigger a set or

reset pulse. The minimum timing between the rising and

falling edges of Clock are determined by the 25K

Ω and 1nF

time constant. That is, the minimum high and low time for

Clock is

≈25 µs.

Micro Processor—The circuit in Figure 9 generates a strong

set/reset pulse (>4 Amp) under microprocessor control. The

SET

RESET

S/R

16V

-16V

≥ 5 µsec

≥ 5 µsec

≈ 2 µsec

5V

set

reset

S/R strap @ 4.5

Ω typ.

3A peak (min.)

SET

10K

1

0.22µF

4.7µF (1)

25K

+16 to 20V

17

HMC2003

2N3904

RESET

S/R

1

2

4

3

5,6

7,8

(1) Tantalum, low R

(2) HEXFETs with

≈0.2Ω Ron

25K

0.1µF

Figure 9—Set/Reset Circuit With Microprocessor Control (1001/1002)

SET and RESET signals are generated from a

microprocessor and control the P and N channel HEXFET

drivers (IRF7105). The purpose of creating the TRS and the

TSR delays are to make sure that one HEXFET is off before

the other one turns on. Basically, a break-before-make

switching pattern. The current pulse is drawn from the 4.7

µF capacitor. If the 5V to 20V converter is used as shown in

Figure 7, then the resultant noise and droop on the 16-20V

supply is not an issue. But if the 16-20V supply is used

elsewhere in the system, then a series dropping resistor

(

≈500Ω) should be placed between the 4.7µF capacitor and

the supply.

Clock

S/R

16V

-16V

≈ 2 µsec

5V

set

reset

Figure 6—Single Clock Set/Reset Timing

Figure 7—5V to 20V Converter

0.22µF*

1

2

8

7

5

SHDN

Vcc

GND

C1-

C1+

1µF

Vout

4

3

C2+

C2-

0.22µF*

1µF

1N5818

20V

6

5V

MAX662A

* Use tantalum capacitors

12V

2µF

1µF

10K

25K

+16 to 20V

2N3904

25K

0.1µF

S/R strap @ 4.5

Ω typ.

3A peak (min.)

Clock

1

0.22µF (2)

4.7µF (3)

17

HMC2003

S/R

(1) HEXFETs with

≈0.2Ω Ron

(2) 0.22µF Tantalum or a

0.68 µF Ceramic CK06

(3) Tantalum, low R

25K

25K

1nF

1nF

8

94

3

2

1

6

5

7

14

5V

74HC04

1N4001

1

2

4

3

5,6

7,8

Figure 8—Single Clock Set/Reset Pulse Circuit (1001/1002)

*

*

•HMC2003 contains one HMC1001 and one HMC1002; together they make the 3-axis sensor.

Three S/R straps are in serial, the total resistance is ~4.5

Ω.