Electronic Components Datasheet Search |
|
MC100EL34D Datasheet(PDF) 1 Page - ON Semiconductor |
|
MC100EL34D Datasheet(HTML) 1 Page - ON Semiconductor |
1 / 8 page © Semiconductor Components Industries, LLC, 2000 October, 2000 – Rev. 3 1 Publication Order Number: MC10EL34/D MC10EL34, MC100EL34 5VECL ÷2, ÷4, ÷8 Clock Generation Chip The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. Upon startup, the internal flip-flops will attain a random state; the master reset (MR) input allows for the synchronization of the internal dividers, as well as multiple EL34s in a system. The 100 Series contains temperature compensation. • 50 ps Output-to-Output Skew • Synchronous Enable/Disable • Master Reset for Synchronization • ESD Protection: > 1 KV HBM, > 100 V MM • PECL Mode Operating Range: V CC= 4.2 V to 5.7 V with VEE= 0 V • NECL Mode Operating Range: V CC= 0 V with VEE= –4.2 V to –5.7 V • Internal Input Pulldown Resistors on CLK(s), EN, and MR • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test • Moisture Sensitivity Level 1 For Additional Information, see Application Note AND8003/D • Flammability Rating: UL–94 code V–0 @ 1/8”, Oxygen Index 28 to 34 • Transistor Count = 191 devices SO–16 D SUFFIX CASE 751B http://onsemi.com 1 16 MARKING DIAGRAMS 1 16 10EL34 AWLYWW A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week Device Package Shipping ORDERING INFORMATION MC10EL34D SO–16 48 Units / Rail MC10EL34DR2 SO–16 2500 Units / Reel MC100EL34D SO–16 48 Units / Rail MC100EL34DR2 SO–16 2500 Units / Reel 1 16 100EL34 AWLYWW |
Similar Part No. - MC100EL34D |
|
Similar Description - MC100EL34D |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |