MPC106 PCI Bridge/Memory Controller Hardware Specifications

11

Electrical and Thermal Characteristics

Table 8. Output AC Timing Specifications

Num

Characteristic

66 MHz

83.3 MHz

Notes

Min

Max

Min

Max

12

SYSCLK to output driven (output

enable time)

2.0

—

2.0

—

1

13a

SYSCLK to output valid for TS and

ARTRY

—

7.0

—

6.0

2, 3, 4

13b

SYSCLK to output valid for all non-PCI

signals except TS, ARTRY, RAS[0–7],

CAS[0–7], and DWE[0-2]

—

7.0

—

6.0

2, 3, 5

14a

SYSCLK to output valid (for RAS[0–7]

and CAS[0–7])

—

7.0

—

6.0

2, 3

14b

SYSCLK to output valid for PCI signals

—

11.0

—

11.0

3, 6

15a

SYSCLK to output invalid for all

non-PCI signals (output hold)

1.0

—

1.0

—

7, 10

15b

SYSCLK to output invalid for PCI

signals (output hold)

1.0

—

1.0

—

7

18

SYSCLK to ARTRY high impedance

before precharge (output hold)

—

8.0

—

8.0

1

19

SYSCLK to ARTRY precharge enable

(0.4 *

—

(0.4 x

—

8, 1

21

SYSCLK to ARTRY high impedance

after precharge

—

(1.5 *

—

(1.5 x

8, 1

Notes:

V or 2.0 V) of the signal in question. Both input and output timings are measured at the pin (see Figure 5).

driving them.

numbers given in the table must be multiplied by the period of SYSCLK to compute the actual time duration (in

nanoseconds) of the parameter in question.

approaches the PCI-specified allowance of 2ns may not work with the MPC106. For workarounds, see Motorola

application note Designing PCI 2.1-Compliant MPC106 Systems (order number AN1727/D).