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LT1055 Datasheet(PDF) 3 Page - Linear Technology

Part No. LT1055
Description  Precision, High Speed, JFET Input Operational Amplifiers
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Maker  LINER [Linear Technology]
Homepage  http://www.linear.com
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 3 page
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3
LT1055/LT1056
LT1055AM
LT1055M
LT1056AM
LT1056M
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
VOS
Input Offset Voltage (Note1)
LT1055
q
180
500
250
1200
µV
LT1056
q
180
550
250
1250
µV
Average Temperature
(Note 5)
q
1.3
4.0
1.8
8.0
µV/°C
Coefficient of Input Offset
Voltage
IOS
Input Offset Current
Warmed Up
LT1055
q
0.20
1.2
0.25
1.8
nA
TA = 125°C
LT1056
q
0.25
1.5
0.30
2.4
nA
IB
Input Bias Current
Warmed Up
LT1055
q
±0.4
±2.5
±0.5
±4.0
nA
TA = 125°C
LT1056
q
±0.5
±3.0
±0.6
±5.0
nA
AVOL
Large-Signal Voltage Gain
VO = ±10V, RL = 2k
q
40
120
35
120
V/mV
CMRR
Common-Mode Rejection Ratio
VCM = ±10.5V
q
85
100
—8298
dB
PSRR
Power Supply Rejection Ratio
VS = ±10V to ±17V
q
88
104
86
102
dB
VOUT
Output Voltage Swing
RL = 2k
q
±12
±12.9
±12
±12.9
V
ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
VOS
Input Offset Voltage (Note1)
LT1055 H Package
q
100
330
140
750
µV
LT1056 H Package
q
100
360
140
800
µV
LT1055 N8 Package
q
250
1250
µV
LT1056 N8 Package
q
280
1350
µV
Average Temperature
H Package (Note 5)
q
1.2
4.0
1.6
8.0
µV/°C
Coefficient of Input Offset
N8 Package (Note 5)
q
3.0
12.0
µV/°C
Voltage
IOS
Input Offset Current
Warmed Up
LT1055
q
—10
50
1680
pA
TA = 70°C
LT1056
q
14
70—18
100
pA
IB
Input Bias Current
Warmed Up
LT1055
q
±30
±150
±40
±200
pA
TA = 70°C
LT1056
q
±40
±80
±50
±240
pA
AVOL
Large-Signal Voltage Gain
VO = ±10V, RL = 2k
q
80
250
60
250
V/mV
CMRR
Common-Mode Rejection Ratio
VCm = ±10.5V
q
85
100
—8298
dB
PSRR
Power Supply Rejection Ratio
VS = ±10V to ±18V
q
89
105
87
103
dB
VOUT
Output Voltage Swing
RL = 2k
q
±12
±13.1
±12
±13.1
V
LT1055AC
LT1056AC
VS = ±15V, VCM = 0V, –55°C ≤ TA ≤ 125°C unless otherwise noted.
The q denotes specifications which apply over the full operating
temperature range.
For MIL-STD components, please refer to LTC883 data sheet for test
listing and parameters.
Note 1: Offset voltage is measured under two different conditions:
(a) approximately 0.5 seconds after application of power; (b) at TA = 25°C
only, with the chip heated to approximately 38
°C for the LT1055 and to
45
°C for the LT1056, to account for chip temperature rise when the device
is fully warmed up.
Note 2: 10Hz noise voltage density is sample tested on every lot of A
grades. Devices 100% tested at 10Hz are available on request.
Note 3: This parameter is tested on a sample basis only.
Note 4: Current noise is calculated from the formula: in = (2qlB)
1/2, where
q = 1.6
× 10–19 coulomb. The noise of source resistors up to 1GΩ
swamps the contribution of current noise.
Note 5: Offset voltage drift with temperature is practically unchanged when
the offset voltage is trimmed to zero with a 100k potentiometer between
the balance terminals and the wiper tied to V+. Devices tested to tighter
drift specifications are available on request.
LT1055CH/LT1056CH
LT1055CN8/LT1056CN8
VS = ±15V, VCM = 0V, 0°C ≤ TA ≤ 70°C unless otherwise noted.




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