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M1026-1Z-167.3280 Datasheet(PDF) 2 Page - Integrated Circuit Systems |
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M1026-1Z-167.3280 Datasheet(HTML) 2 Page - Integrated Circuit Systems |
2 / 14 page M1025/26 Datasheet Rev 1.0 2 of 14 Revised 28Jul2004 I n te g r at ed Ci rcui t Systems , In c. ● N e tw o r ki ng & Co mmun ica t io ns ● ww w. icst.co m ● tel (5 08 ) 85 2-5 4 0 0 Integrated Circuit Systems, Inc. M1025/26 VCSO BASED CLOCK PLL WITH AUTOSWITCH Prod uct Data Sh eet PIN DESCRIPTIONS Number Name I/O Configuration Description 1, 2, 3, 10, 14, 26 GND Ground Power supply ground connections. 4 9 OP_IN nOP_IN Input External loop filter connections. See Figure 5, External Loop Filter, on pg. 9. 5 8 nOP_OUT OP_OUT Output 6 7 nVC VC Input 11, 19, 33 VCC Power Power supply connection, connect to +3.3V. 12 AUTO Input Internal pull-down resistor1 Automatic/manual reselection mode for clock input: Logic 1 automatic reselection upon clock failure (non-revertive) Logic 0 manual selection only (using REF_SEL) 13 REF_ACK Output Reference Acknowledgement pin for input mux state; outputs the currently selected reference input pair: Logic 1 indicates nDIF_REF1, DIF_REF1 Logic 0 indicates nDIF_REF0, DIF_REF0 15 16 FOUT nFOUT Output No internal terminator Clock output pair. Differential LVPECL (CML, LVDS available). 17 18 P_SEL1 P_SEL0 Internal pull-down resistor1 Note 1: For typical values of internal pull-down and pull-UP resistors, see DC Characteristics on pg. 11. Post-PLL , P divider selection. LVCMOS/LVTTL. See Table 5, P Divider Look-Up Table (LUT), on pg. 4. 20 nDIF_REF1 Input Biased to Vcc/2 2 Note 2: Biased toVcc/2, with 50k Ω to Vcc and 50kΩ to ground. See Differential Inputs Biased to VCC/2 on pg. 11. Reference clock input pair 1. Differential LVPECL or LVDS. Resistor bias on inverting terminal supports TTL or LVCMOS. 21 DIF_REF1 Internal pull-down resistor1 22 REF_SEL Input Internal pull-down resistor1 Reference clock input selection. LVCMOS/LVTTL: Logic 1 selects DIF_REF1, nDIF_REF1. Logic 0 selects DIF_REF0, nDIF_REF0. 23 nDIF_REF0 Input Biased to Vcc/2 2 Reference clock input pair 0. Differential LVPECL or LVDS. Resistor bias on inverting terminal supports TTL or LVCMOS. 24 DIF_REF0 Internal pull-down resistor 1 25 NC No internal connection. 27 28 29 30 MR_SEL3 MR_SEL2 MR_SEL0 MR_SEL1 Input Internal pull-down resistor1 M and R divider value selection. LVCMOS/ LVTTL. See Tables 3 and 4, M and R Divider Look-Up Tables (LUT) on pg. 3. 31 LOL Output Loss of Lock indicator output. Asserted when internal PLL is not tracking the input reference for frequency and phase. 3 Logic 1 indicates loss of lock. Logic 0 indicates locked condition. Note 3: See LVCMOS Output in DC Characteristics on pg. 11. 32 NBW Input Internal pull-UP resistor1 Narrow Bandwidth enable. LVCMOS/LVTTL: Logic 1 - Narrow loop bandwidth, R IN = 2100k Ω. Logic 0 - Wide bandwidth, R IN = 100k Ω. 34, 35, 36 DNC Do Not Connect. Table 2: Pin Descriptions |
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