M1025/26 Datasheet Rev 1.0

2 of 14

Revised 28Jul2004

Integrated

Circuit

Systems, Inc.

M1025/26

Prod uct Data Sh eet

Number

Name

I/O

Configuration

Description

1, 2, 3, 10, 14, 26

GND

Ground

Power supply ground connections.

4

9

OP_IN

nOP_IN

Input

External loop filter connections.

See Figure 5, External Loop Filter, on pg. 9.

5

8

nOP_OUT

OP_OUT

Output

6

7

nVC

VC

Input

11, 19, 33

VCC

Power

12

AUTO

Input

Automatic/manual reselection mode for clock input:

(non-revertive)

13

REF_ACK

Output

Reference Acknowledgement pin for input mux state; outputs

the currently selected reference input pair:

15

16

FOUT

nFOUT

Output

No internal terminator

Clock output pair. Differential LVPECL (CML, LVDS available).

17

18

P_SEL1

P_SEL0

Note 1: For typical values of internal pull-down and pull-UP resistors, see

DC Characteristics on pg. 11.

Post-PLL , P divider selection. LVCMOS/LVTTL. See Table 5,

P Divider Look-Up Table (LUT), on pg. 4.

20

nDIF_REF1

Input

Note 2: Biased toVcc/2, with 50k

Ω to Vcc and 50kΩ to ground. See Differential Inputs Biased to VCC/2 on pg. 11.

Reference clock input pair 1. Differential LVPECL or LVDS.

Resistor bias on inverting terminal supports TTL or LVCMOS.

21

DIF_REF1

22

REF_SEL

Input

Reference clock input selection. LVCMOS/LVTTL:

23

nDIF_REF0

Input

Reference clock input pair 0. Differential LVPECL or LVDS.

Resistor bias on inverting terminal supports TTL or LVCMOS.

24

DIF_REF0

25

NC

No internal connection.

27

28

29

30

MR_SEL3

MR_SEL2

MR_SEL0

MR_SEL1

Input

M and R divider value selection. LVCMOS/ LVTTL.

See Tables 3 and 4, M and R Divider Look-Up Tables (LUT)

on pg. 3.

31

LOL

Output

Loss of Lock indicator output. Asserted when internal PLL is

Note 3: See LVCMOS Output in

DC Characteristics on pg. 11.

32

NBW

Input

Narrow Bandwidth enable. LVCMOS/LVTTL:

Ω.

Ω.

34, 35, 36

DNC

Do Not Connect.

Table 2: Pin Descriptions