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CY7C1338 3 Pin Descriptions Pin Number Name I/O Description 85 ADSC Input- Synchronous Address Strobe from Controller, sampled on the rising edge of CLK. When asserted LOW, A[16:0] is captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. 84 ADSP Input- Synchronous Address Strobe from Processor, sampled on the rising edge of CLK. When asserted LOW, A[16:0] is captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. 36, 37 A[1:0] Input- Synchronous A1, A0 Address Inputs. These inputs feed the on-chip burst counter as the LSBs as well as being used to access a particular memory location in the memory array. 49 −44, 81–82, 99–100, 32–35 A[16:2] Input- Synchronous Address Inputs used in conjunction with A[1:0] to select one of the 64K address loca- tions. Sampled at the rising edge of the CLK, if CE1, CE2, and CE3 are sampled active, and ADSP or ADSC is active LOW. 96–93 BW[3:0] Input- Synchronous Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes. Sampled on the rising edge. BW0 controls DQ[7:0] and DP0, BW1 controls DQ[15:8] and DP1, BW2 controls DQ[23:16] and DP2, and BW3 controls DQ[31:24] and DP3. See Write Cycle Descriptions table for further details. 83 ADV Input- Synchronous Advance Input used to advance the on-chip address counter. When LOW the internal burst counter is advanced in a burst sequence. The burst sequence is selected using the MODE input. 87 BWE Input- Synchronous Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a byte write. 88 GW Input- Synchronous Global Write Input, active LOW. Sampled on the rising edge of CLK. This signal is used to conduct a global write, independent of the state of BWE and BW[3:0]. Global writes override byte writes. 89 CLK Input-Clock Clock Input. Used to capture all synchronous inputs to the device. 98 CE1 Input- Synchronous Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in con- junction with CE2 and CE3 to select/deselect the device. CE1 gates ADSP. 97 CE2 Input- Synchronous Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in con- junction with CE1 and CE3 to select/deselect the device. 92 CE3 Input- Synchronous Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in con- junction with CE1 and CE2 to select/deselect the device. 86 OE Input- Asynchronous Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. 64 ZZ Input- Asynchronous Snooze Input. Active HIGH asynchronous. When HIGH, the device enters a low-power standby mode in which all other inputs are ignored, but the data in the memory array is maintained. Leaving ZZ floating or NC will default the device into an active state. ZZ pin has an internal pull-down. 31 MODE - Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order. Pulled LOW selects the linear burst order. When left floating or NC, de- faults to interleaved burst order. Mode pin has an internal pull-up. 29–28, 25–22, 19–18, 13–12, 9–6, 3–2, 79–78, 75–72, 69–68, 63–62, 59–56, 53–52 DQ[31:0] I/O- Synchronous Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A[16:0] during the previous clock rise of the read cycle. The direction of the pins is controlled by OE in conjunction with the internal control logic. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQ[31:0] and DP[3:0] are placed in a three-state condition. The outputs are automatically three-stated when a WRITE cycle is detected. 15, 41, 65, 91 VDD Power Supply Power supply inputs to the core of the device. Should be connected to 3.3V power supply. |
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