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IDT7134LA25L48 Datasheet(PDF) 9 Page - Integrated Device Technology |
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IDT7134LA25L48 Datasheet(HTML) 9 Page - Integrated Device Technology |
9 / 11 page 9 IDT7134SA/LA High-Speed 4K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges 2720 drw 10 R/ W "A"(1) VALID tWC MATCH VALID MATCH tWP tDW tWDD tDDD ADDR "A" DATAIN "A" DATAOUT "B" ADDR "B" tAW Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8) Timing Waveform of Write with Port-to-Port Read(1,2,3) NOTES: 1. Write cycle parameters should be adhered to, in order to ensure proper writing. 2. CEL = CER = VIL. OE"B" = VIL. 3. Port "A" may be either left or right port. Port "B" is the opposite from port "A". NOTES: 1. R/W or CE must be HIGH during all address transitions. 2. A write occurs during the overlap (tEW or tWP) of a CE =VIL and R/W = VIL. 3. tWR is measured from the earlier of CE or R/W going to VIH to the end-of-write cycle. 4. During this period, the I/O pins are in the output state, and input signals must not be applied. 5. If the CE = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal (CE or R/W) is asserted last. 7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured +500mV from steady state with the Output Test Load (Figure 2). 8. If OE = VIL during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. CE 2720 drw 11 tAW tAS(6) tDW DATAIN ADDRESS tWC R/ W tWP DATAOUT tWZ (7) (4) (4) (2) OE tHZ (7) tLZ (7) tHZ tWR (3) (7) tDH tOW |
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