TLK4120

QUAD 0.5 to 1.3 Gbps TRANSCEIVER

SLLS599C − DECEMBER 2003 − REVISED JULY 2006

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start/stop framing logic (continued)

...

Start

Bit

Stop

Bit

TDx0

TDx1

TDx16 TDx17

Start

Bit

Stop

Bit

20-Bit Frame

18-Bit Word

Figure 3. Serial Output Data Stream With Start and Stop Bit

parallel-to-serial

The parallel-to-serial shift register takes in the 20-bit wide frame multiplexed from the framing logic and converts

it to a serial stream. The shift register is clocked on both the rising and falling edges of the internally generated

bit clock, which is 10 times the GTx_CLK input frequency. The LSB (TDx0) is first out after the start bit as shown

in Figure 3.

high-speed data output

The high-speed data output driver consists of a PECL-compatible differential pair that can be optimized for a

particular transmission line impedance and length. The line can be directly coupled or ac coupled. See Figure 10

and Figure 11 for termination details. No external pullup or pulldown resistors are required.

The TLK4120 provides a selectable signal preemphasis option for driving lossy media. When signal

preemphasis is enabled, the first bit of a run length of same-value bits (e.g., 111...) is driven to a larger output

swing, which precompensates for signal inter-symbol interference (ISI) in lossy media, such as copper cables

or printed circuit board traces.

receive interface

The receiver portion of the TLK4120 accepts 20-bit framed differential serial data. The interpolator and clock

recovery circuit locks to the data stream and extracts the bit rate clock. This recovered clock is used to retime

the input data stream. The serial data is then aligned to the 20-bit frame by finding the start and stop bits and

the 18-bit data is output on a 18-bit wide parallel bus synchronized to the extracted receive clock (Rx_CLK).

receive data bus

The receive bus interface drives 18-bit wide single-ended TTL parallel data at the RDx[0:17] terminals. Data

is valid on the rising edge of Rx_CLK. The Rx_CLK is used as the recovered word clock. The data and clock

signals are aligned as shown in Figure 4. Detailed timing information can be found in the TTL output switching

characteristics table.

Rx_CLK

RDx[0:17]

tsu

th

Figure 4. Receive Timing Waveform