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WM8152SCDS Datasheet(PDF) 11 Page - Wolfson Microelectronics plc |
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WM8152SCDS Datasheet(HTML) 11 Page - Wolfson Microelectronics plc |
11 / 26 page Production Data WM8152 w PD Rev 4.0 January 2004 11 TIMING CONTROL S/H 4-BIT RLC DAC CL + + - TO OFFSET DAC RLC CDS FROM CONTROL INTERFACE S/H V S R S FROM CONTROL INTERFACE MCLK VSMP INPUT SAMPLING BLOCK CDS C IN VINP VRLC/ VBIAS 2 1 EXTERNAL VRLC VRLCEXT Figure 4 Reset Level Clamping and CDS Circuitry Reset Level Clamping is controlled by register bit RLCINT. Figure 5 illustrates the effect of the RLCINT bit for a typical CCD waveform, with CL applied during the reset period. The RLCINT register bit is sampled on the positive edge of MCLK that occurs during each VSMP pulse. The sampled level, high (or low) controls the presence (or absence) of the internal CL pulse on the next reset level. The position of CL can be adjusted by using control bits CDSREF[1:0] (Figure 6). MCLK VSMP ACYC/RLC or RLCINT CL (CDSREF = 01) INPUT VIDEO 1X X 0 X X 0 RGB RGB No RLC on this Pixel RLC on this Pixel Programmable Delay RGB Figure 5 Relationship of RLCINT, MCLK and VSMP to Internal Clamp Pulse, CL The VRLC/VBIAS pin can be driven internally by a 4-bit DAC (RLCDAC) by writing to control bits RLCV[3:0]. The RLCDAC range and step size may be increased by writing to control bit RLCDACRNG. Alternatively, the VRLC/VBIAS pin can be driven externally by writing to control bit VRLCEXT to disable the RLCDAC and then applying a d.c. voltage to the pin. CDS/NON-CDS PROCESSING For CCD type input signals, the signal may be processed using CDS, which will remove pixel-by-pixel common mode noise. For CDS operation, the video level is processed with respect to the video reset level, regardless of whether RLC has been performed. To sample using CDS, control bit CDS must be set to 1 (default), this controls switch 2 (Figure 4) and causes the signal reference to come from the video reset level. The time at which the reset level is sampled, by clock Rs/CL, is adjustable by programming control bits CDSREF[1:0], as shown in Figure 6. |
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