Philips Semiconductors

Product specification

PZ3032

32 macrocell CPLD

2

1997 Feb 20

853–1852 17780

FEATURES

process technologies

power and very high speed

devices

macrocells are fixed

extreme flexibility

CAE tools

product terms in each logic block for:

– Programmable 3-State buffer

– Asynchronous macrocell register preset/reset

without using logic resources

Table 1. PZ3032 Features

PZ3032

Usable gates

1000

Maximum inputs

36

Maximum I/Os

32

Number of macrocells

32

I/O macrocells

32

Buried macrocells

0

Propagation delay (ns)

8.0

Packages

44-pin PLCC, 44-pin TQFP

DESCRIPTION

The PZ3032 CPLD (Complex Programmable Logic Device) is the

first in a family of Fast Zero Power (FZP

™) CPLDs from Philips

Semiconductors. These devices combine high speed and zero

power in a 32 macrocell CPLD. With the FZP

™ design technique,

the PZ3032 offers true pin-to-pin speeds of 8ns, while

simultaneously delivering power that is less than 35

µA at standby

without the need for ‘turbo bits’ or other power down schemes. By

replacing conventional sense amplifier methods for implementing

product terms (a technique that has been used in PLDs since the

bipolar era) with a cascaded chain of pure CMOS gates, the

dynamic power is also substantially lower than any competing CPLD

– 70% lower at 50MHz. These devices are the first TotalCMOS

™

PLDs, as they use both a CMOS process technology and the

patented full CMOS FZP

™ design technique. For 5V applications,

Philips also offers the high speed PZ5032 CPLD that offers

pin-to-pin speeds of 6ns.

The Philips FZP

™ CPLDs introduce the new patent-pending XPLA™

(eXtended Programmable Logic Array) architecture. The XPLA

™

architecture combines the best features of both PLA and PAL

™ type

structures to deliver high speed and flexible logic allocation that

results in superior ability to make design changes with fixed pinouts.

The XPLA

™ structure in each logic block provides a fast 8ns PAL™

path with 5 dedicated product terms per output. This PAL

™ path is

joined by an additional PLA structure that deploys a pool of 32

product terms to a fully programmable OR array that can allocate

the PLA product terms to any output in the logic block. This

combination allows logic to be allocated efficiently throughout the

logic block and supports as many as 37 product terms on an output.

The speed with which logic is allocated from the PLA array to an

output is only 2.5ns, regardless of the number of PLA product terms

to any other pin. In addition, logic that is common to multiple outputs

can be placed on a single PLA product term and shared across

multiple outputs via the OR array, effectively increasing design

density.

The PZ3032 CPLDs are supported by industry standard CAE tools

(Cadence, Mentor, Synopsys, Synario, Viewlogic, OrCAD), using

text (Abel, VHDL, Verilog) and/or schematic entry. Design

verification uses industry standard simulators for functional and

timing simulation. Development is supported on personal computer,

Sparc, and HP platforms. Device fitting uses either Minc or Philips

Semiconductors-developed tools.

The PZ3032 CPLD is reprogrammable using industry standard

device programmers from vendors such as Data I/O, BP

Microsystems, SMS, and others.

PAL is a registered trademark of Advanced Micro Devices, Inc.