Philips Semiconductors

Product specification

PZ3032

32 macrocell CPLD

1997 Feb 20

6

Simple Timing Model

Figure 4 shows the CoolRunner

™ Timing Model. The CoolRunner™

timing model looks very much like a 22V10 timing model in that

In other competing architectures, the user may be able to fit the

design into the CPLD, but is not sure whether system timing

requirements can be met until after the design has been fit into the

device. This is because the timing models of competing

architectures are very complex and include such things as timing

dependencies on the number of parallel expanders borrowed,

sharable expanders, varying number of X and Y routing channels

used, etc. In the XPLA

™ architecture, the user knows up front

whether the design will meet system timing requirements. This is

due to the simplicity of the timing model. For example, in the

PZ3032 device, the user knows up front that if a given output uses 5

account for the time to propagate through the PLA array.

TotalCMOS

™ Design Technique

for Fast Zero Power

Philips is the first to offer a TotalCMOS

™ CPLD, both in process

technology and design technique. Philips employs a cascade of

CMOS gates to implement its Sum of Products instead of the

traditional sense amp approach. This CMOS gate implementation

allows Philips to offer CPLDs which are both high performance and

low power, breaking the paradigm that to have low power, you must

vs. Frequency of our PZ3032 TotalCMOS

™ CPLD.

OUTPUT PIN

INPUT PIN

SP00441

CLOCK

OUTPUT PIN

INPUT PIN

DQ

REGISTERED

REGISTERED

Figure 4.

CoolRunner

™ Timing Model

0

5

10

15

20

25

30

0

10

20

30

40

50

60

70

80

90

100

110

120

130

TYPICAL

(mA)

FREQUENCY (MHz)

SP00443

Figure 5.

FREQ

(MHz)

0

10

20

30

40

50

60

70

80

90

100

110

120

130

Typical

0.01

2.37

4.65

6.80

9.06

11.1

13.5

15.5

17.4

20.0

22.1

24.4

26.6

28.5