HY67V161610DTC-5 datasheet(8/11 Pages) HYNIX

Part #	HY67V161610DTC-5

Description	2 Banks x 512K x 16 Bit Synchronous DRAM

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Manufacturer	HYNIX [Hynix Semiconductor]

Direct Link	http://www.skhynix.com/kor/main.do

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8 / 11 page

HY57V161610D

Rev. 3.6/Apr.01

8

AC CHARACTER IST ICS

(TA=0

°C to 70 °C , V DD =3.0V to 3.6V, V SS =0V Note1,2 ))

Note :

1. V DD (min) is 3.15V when HY57V161610DTC-7 operates at CAS latency=2 and tCK2=8.9ns.

2.V DD (min) of HY57V161610DTC-5/55 is 3.15V

3. A new command can be given tRRC after self refresh exit.

Paramter

Symbol

-5

-55

-6

-7

-8

-10

Un it

Note

M in

Max

M in

Max

M in

Ma

x

Min

Ma

x

M in

Ma

x

M in

Ma

x

RAS cycle time

Operation

tRC

55

60

-

70

-

70

-

70

-

ns

Auto Refresh

tRRC

55

60

-

70

-

70

-

80

-

ns

RAS to CAS delay

tRCD

15

16.5

18

-

20

-

20

-

20

-

ns

RAS active time

tRAS

40

100

K

38.5

100

K

40

100

K

45

100

K

45

100

K

45

100

K

ns

RAS precharge time

tRP

3

-

3

-

3

-

2

-

CLK

RAS to RAS bank active delay

tRRD

2

-

2

-

2

-

2

-

CLK

CAS to CAS bank active delay

tCCD

1

-

1

-

1

-

1

-

CLK

Write command to data-in delay

tWTL

0

-

0

-

0

-

0

-

CLK

Data-in to precharge command

tDPL

1

-

1

-

1

-

1

-

CLK

Data-in to active command

tDAL

4

-

4

-

4

-

3

-

CLK

DQM to data-in Hi-Z

tDQZ

2

-

2

-

2

-

2

-

CLK

DQM to data mask

tDQM

0

-

0

-

0

-

0

-

CLK

MRS to new command

tMRD

2

-

2

-

2

-

2

-

CLK

Precharge to data output Hi-Z

tPROZ

3

-

3

-

3

-

3

-

CLK

Power down exit time

tPDE

1

-

1

-

1

-

1

-

CLK

Self refresh exit time

tSRE

1

-

1

-

1

-

1

-

CLK

3

Refresh Time

tREF

64

-

64

-

64

-

64

-

ms

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