© 2006 Fairchild Semiconductor Corporation

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FMS6502 Rev. 1.0.0

7

Figure 4.

Bit Transfer

Operation

cation for Standard Mode. Individual addresses may be

written, but there is no read capability. The interface con-

sists of two lines: a serial data line (SDA) and a serial

clock line (SCL). Both lines must be connected to a posi-

tive supply through an external resistor. Data transfer

may be initiated only when the bus is not busy.

Bit Transfer

One data bit is transferred during each clock pulse. The

data on the SDA line must remain stable during the

HIGH period of the clock pulse. Changes in the data line

during this time are interpreted as control signals.

Data line

stable;

data valid

SCL

SDA

Change

of data

allowed

Start and Stop conditions

Both data and clock lines remain HIGH when the bus is

not busy. A HIGH-to-LOW transition of the data line,

while the clock is HIGH, is defined as start condition (S).

A LOW-to-HIGH transition of the data line, while the

clock is HIGH, is defined as stop condition (P).

Figure 5. START and STOP conditions

SP

START condition

STOP condition

SCL

SDA