K4C89323AF-GCF5 datasheet(9/58 Pages) SAMSUNG

Part #	K4C89323AF-GCF5

Description	2,097,152-WORDS x 4 BANKS x 36-BITS DOUBLE DATA RATE Network-DRAM

Download	58 Pages

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Manufacturer	SAMSUNG [Samsung semiconductor]

Direct Link	http://www.samsung.com/Products/Semiconductor

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9 / 58 page

K4C89363AF

REV. 0.0 Nov. 2002

- 9 -

AC Characteristics and Operating Conditions (Notes : 1, 2)

Symbol

Parameter

F6

FB

F5

Units

Notes

Min

Max

Min

Max

Min

Max

t RC

Random Cycle Time

20.0

-

22.5

-

25

-

ns

3

t CK

Clock Cycle Time

C

L = 4

4.0

7.5

4.5

7.5

5.0

7.5

3

C

L

= 5

3.33

7.5

3.75

7.5

4.5

7.5

3

C

L = 6

3.0

7.5

3.33

7.5

4.0

7.5

3

t RAC

Random Access Time

-

20.0

-

22.5

-

25

3

t CH

Clock High Time

0.45*t

CK

-

0.45*t

CK

-

0.45*t

CK

-

3

t CL

Clock Low Time

0.45*t

CK

-

0.45*t

CK

-

0.45*t

CK

-

3

t CKQS

QS Access Time from CLK

-0.45

0.45

-0.45

0.45

-0.5

0.5

3, 8

t QSQ

Data Output Skew from QS

-

0.2

-

0.25

-

0.3

4

t AC

Data Access Time from CLK

-0.5

0.5

-0.5

0.5

-0.6

0.6

3, 8

t OH

Data Output Hold Time from CLK

-0.5

0.5

-0.5

0.5

-0.6

0.6

3, 8

t HP

CLK half period ( minium of Actual t

CH , t CL )

min(t

CH , t CL )

-

min(t

CH , tCL )

-

min(t

CH , t CL )

-

3

t QSP

QS(Read) Pulse Width

t HP-t QHS

-

t HP-tQHS

-

t HP-t QHS

-

4, 8

t QSQV

Data Output Valid Time from QS

t HP-t QHS

-

t HP-tQHS

-

t HP-t QHS

-

4, 8

t QHS

DQ, QS Hold skew factor

-

0.055x

t CK+0.17

-

0.055x

tCK+0.17

-

0.055x

t CK+0.17

t DQSS

DS(Write) Low to High Setup Time

0.8*t

CK

1.2*t

CK

0.8*t

CK

1.2*t

CK

0.8*t

CK

1.2*t

CK

3

t DSPRE

DS(Write) Preamble Pulse Width

0.4*t

CK

-

0.4*t

CK

-

0.4*t

CK

-

4

t DSPRES

DS First Input Setup Time

0

-

0

-

0

-

3

t DSPREH

DS First Low Input Hold Time

0.3*t

CK

-

0.3*t

CK

-

0.3*t

CK

-

3

t DSP

DS High or Low Input Pulse Width

0.45*t

CK

0.55*t

CK

0.45*t

CK

0.55*t

CK

0.45*t

CK

0.55*t

CK

4

t DSS

DS Input Falling Edge to Clock Setup Time

C

L

= 4

0.9

-

0.9

-

1.0

-

3, 4

C

L = 5

0.9

-

0.9

-

1.0

-

3, 4

C

L = 6

0.9

-

0.9

-

1.0

-

3, 4

t DSPST

DS(Write) Postamble Pulse Width

0.45*t

CK

-

0.45*t

CK

0.45*t

CK

-

4

t DSPSTH

DS(Write) Postamble Hold Time

C

L

= 4

0.9

-

0.9

-

1.0

-

3, 4

C

L = 5

0.9

-

0.9

-

1.0

-

3, 4

C

L = 6

0.9

-

0.9

-

1.0

3, 4

t DS

Data Input Setup Time from DS

0.3

-

0.35

-

0.4

-

4

t DH

Data Input Hold Time from DS

0.3

-

0.35

-

0.4

-

4

t IS

Command / Address Input Setup Time

0.6

-

0.6

-

0.7

-

3

t IH

Command / Address Input Hold Time

0.6

-

0.6

-

0.7

-

3

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