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ISPLSI1016E125LT44 Datasheet(PDF) 8 Page - Lattice Semiconductor |
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ISPLSI1016E125LT44 Datasheet(HTML) 8 Page - Lattice Semiconductor |
8 / 15 page 8 1996 ISP Encyclopedia Specifications ispLSI and pLSI 1016E ispLSI and pLSI 1016E Timing Model GLB Reg Delay I/O Pin (Output) ORP Delay Feedback Reg 4 PT Bypass 20 PT XOR Delays Control PTs Input Register Clock Distribution I/O Pin (Input) Y0 Y1,2 D Q GLB Reg Bypass ORP Bypass DQ RST RE OE CK I/O Reg Bypass I/O Cell ORP GLB GRP I/O Cell #23 - 27 #30 #35 #36-38 #55-58 #44-46 #54 #47 #48 Reset Ded. In GOE 0 #28 #22 RST #59 #59 #39 #40-43 #51, 52 0491-16 Comb 4 PT Bypass #34 #53 GRP Loading Delay #29, 31, 32 #49, 50 Derivations of tsu, th and tco from the Product Term Clock1 = = = = tsu Logic + Reg su - Clock (min) ( tiobp + tgrp4 + t20ptxor) + (tgsu) - (tiobp + tgrp4 + tptck(min)) (#22 + #30 + #37) + (#40) - (#22 + #30 + #46) (0.3 + 1.9 + 4.4) + (0.2) - (0.3 + 1.9 + 3.2) 1.4 ns = = = = th Clock (max) + Reg h - Logic ( tiobp + tgrp4 + tptck(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor) (#22 + #30 + #46) + (#41) - (#22 + #30 + #37) (0.3 + 1.9 + 3.5) + (1.5) - (0.3 + 1.9 + 4.4) 0.6 ns = = = = tco Clock (max) + Reg co + Output ( tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob) (#22 + #30 + #46) + (#42) + (#47 + #49) (0.3 + 1.9 + 3.5) + (1.8) + (1.0 + 1.4) 9.9 ns Table 2-0042-16 Derivations of tsu, th and tco from the Clock GLB1 = = = = tsu Logic + Reg su - Clock (min) ( tiobp + tgrp4 + t20ptxor) + (tgsu) - (tgy0(min) + tgco + tgcp(min)) (#22 + #30 + #37) + (#40) - (#54 + #42 + #56) (0.3 + 1.9 + 4.4) + (0.2) - (1.3 + 1.8 + 0.8) 2.9 ns = = = = th Clock (max) + Reg h - Logic ( tgy0(max) + tgco + tgcp(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor) (#54 + #42 + #56) + (#41) - (#22 + #30 + #37) (1.3 + 1.8 + 1.8) + (1.5) - (0.3 + 1.9 + 4.4) -0.2 ns = = = = tco Clock (max) + Reg co + Output ( tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob) (#54 + #42 + #56) + (#42) + (#47 + #49) (1.3 + 1.8 + 1.8) + (1.8) + (1.0 + 1.4) 9.1 ns 1. Calculations are based upon timing specifications for the ispLSI and pLSI 1016E- 125 |
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