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K6E1004C1B Datasheet(PDF) 2 Page - Samsung semiconductor

Part No. K6E1004C1B
Description  256Kx4 Bit (with OE) High Speed Static RAM(5V Operating), Evolutionary Pin out
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Maker  SAMSUNG [Samsung semiconductor]
Homepage  http://www.samsung.com/Products/Semiconductor
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K6E1004C1B-C/B-L
CMOS SRAM
PRELIMINARY
Rev. 3.0
- 2 -
July 1998
256K x 4 Bit (with OE)High-Speed CMOS Static RAM
GENERAL DESCRIPTION
FEATURES
• Fast Access Time 15, 20ns(Max.)
• Low Power Dissipation
Standby (TTL)
: 20mA(Max.)
(CMOS) : 5mA(Max.)
1mA(Max) L-Ver. Only
Operating K6E1004C1B-15 : 120mA(Max.)
K6E1004C1B-20 : 118mA(Max.)
• Single 5.0V
±10% Power Supply
• TTL Compatible Inputs and Outputs
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• 2V Minimum Data Retention ; L-Ver. only
• Standard Pin Configuration
K6E1004C1B-J : 28-SOJ-400A
PIN FUNCTION
Pin Name
Pin Function
A0 - A17
Address Inputs
WE
Write Enable
CS
Chip Select
OE
Output Enable
I/O1 ~ I/O4
Data Inputs/Outputs
VCC
Power(+5.0V)
VSS
Ground
N.C
No Connection
The K6E1004C1B is a 1,048,576-bit high-speed Static Random
Access Memory organized as 262,144 words by 4 bits. The
K6E1004C1B uses 4 common input and output lines and has at
output enable pin which operates faster than address access
time at read cycle. The device is fabricated using SAMSUNG
′s
advanced CMOS process and designed for high-speed circuit
technology. It is particularly well suited for use in high-density
high-speed system applications. The K6E1004C1B is packaged
in a 400 mil 28-pin plastic SOJ.
PIN CONFIGURATION(Top View)
Clk Gen.
I/O1~I/O4
CS
WE
OE
FUNCTIONAL BLOCK DIAGRAM
Data
Cont.
Column Select
CLK
Gen.
Pre-Charge Circuit
Memory Array
512 Rows
512x4 Columns
I/O Circuit &
SOJ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
A17
A16
A15
A14
A13
A12
A11
N.C
I/O4
I/O3
I/O2
I/O1
WE
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
CS
OE
Vss
A9 A10 A11 A12 A13 A14 A15 A16 A17
A0
A1
A2
A3
A4
A5
A6
A7
A8




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