K6R1004C1A-C

CMOS SRAM

PRELIMINARY

Rev 4.0

- 2 -

February 1998

256K x 4 Bit (with OE)High-Speed CMOS Static RAM

GENERAL DESCRIPTION

FEATURES

• Fast Access Time 12, 15, 20ns(Max.)

• Low Power Dissipation

Standby (TTL)

: 25mA(Max.)

(CMOS) : 8mA(Max.)

Operating K6R1004C1A-12 : 150mA(Max.)

K6R1004C1A-15 : 145mA(Max.)

K6R1004C1A-20 : 140mA(Max.)

• Single 5.0V

±10% Power Supply

• TTL Compatible Inputs and Outputs

• I/O Compatible with 3.3V Device

• Fully Static Operation

- No Clock or Refresh required

• Three State Outputs

• Center Power/Ground Pin Configuration

• Standard Pin Configuration

K6R1004C1A-J : 32-SOJ-400

The K6R1004C1A is a 1,048,576-bit high-speed Static Random

Access Memory organized as 262,144 words by 4 bits. The

K6R1004C1A uses 4 common input and output lines and has

an output enable pin which operates faster than address

access time at read cycle. The device is fabricated using SAM-

SUNG

′s advanced CMOS process and designed for high-

speed circuit technology. It is particularly well suited for use in

high-density

high-speed

system

applications.

The

K6R1004C1A is packaged in a 400 mil 32-pin plastic SOJ.

PIN FUNCTION

Pin Name

Pin Function

Address Inputs

WE

Write Enable

CS

Chip Select

OE

Output Enable

Data Inputs/Outputs

Power(+5.0V)

Ground

N.C

No Connection

Clk Gen.

CS

WE

OE

FUNCTIONAL BLOCK DIAGRAM

Data

Cont.

Column Select

CLK

Gen.

Pre-Charge Circuit

Memory Array

512 Rows

512x4 Columns

I/O Circuit &

SOJ

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

OE

Vss

Vcc

N.C

N.C

CS

Vcc

Vss

WE

N.C