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Semiconductor Group

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The differential inputs of the IC may be connected either balanced or single ended. In the latter case

the unused input must be RF-grounded with a capacitor (about 1.5 nF) with a low serial inductance.

Depending on the logic level at SW input the basic divide ratio of the ECL-stages is fixed to 1:64/65

or 1:128/129. The MOD input determines whether modulus 1:n or 1:n+1 (n=64 or 128 according to

SW-level) is active.

The IC can be switched to a low-power standby mode (input STB).

The MOD input is TTL/CMOS compatible.

The emitter follower output is CMOS compatible according to the application circuit on page 11. The

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6:

LOW = GND to 0.8 V or open

1:64/65

1:128/129

02'

LOW = GND to 0.8 V

1:64/1:128

1:65/1:129

67%

LOW = GND to 0.8 V

Divider

Q=HIGH, STANDBY-mode