Genesis Microchip
gm5020/gm5020-H Data Sheet
February 2002
C5020-DAT-01Q
vi
4.10.4 SDRAM Power On Sequence .............................................................................. 41
4.10.5 SDRAM Power Down ........................................................................................... 41
4.10.6 Pan and Crop Operations..................................................................................... 42
4.10.7 Double Buffering Frame Store Bandwidth Requirements..................................... 42
4.10.8 Freeze Frame....................................................................................................... 42
4.10.9 Interlaced Formats and De-interlacing ................................................................. 42
4.11 Scaling............................................................................................................................ 43
4.11.1 Pixel Replication Scaling ...................................................................................... 43
4.11.2 Vertical Shrink ...................................................................................................... 43
4.11.3 Adaptive Contrast Enhancement (ACE) ............................................................... 43
4.12 Gamma Correction LUT.................................................................................................. 44
4.12.1 Gamma Correction ............................................................................................... 44
4.12.2 Moiré Cancellation................................................................................................ 45
4.13 Display Timing and Control............................................................................................. 46
4.13.1 Display Clock Generation – Display Digital Direct Synthesis Block (DDDS) ........ 46
4.13.2 Display Synchronization ....................................................................................... 47
4.13.3 Display Port Timing .............................................................................................. 49
4.14 Data Path Bypass Options.............................................................................................. 51
4.15 OSD................................................................................................................................ 53
4.15.1 Character Mapped OSD ....................................................................................... 53
4.15.2 Bitmapped OSD ................................................................................................... 59
4.15.3 Color Look-up Table (LUT)................................................................................... 59
4.15.4 Multiple OSD Windows......................................................................................... 59
4.15.5 OSD Stretch ......................................................................................................... 59
4.15.6 Blending ............................................................................................................... 59
4.15.7 OSD Merge .......................................................................................................... 60
4.16 On-Chip Microprocessor................................................................................................. 61
4.17 Bootstrap Configuration .................................................................................................. 62
4.18 Host Interface ................................................................................................................. 63
4.18.1 2-wire Configuration ............................................................................................. 63
4.18.2 6-Wire Configuration ............................................................................................ 66
4.19 Miscellaneous Functions ................................................................................................ 69
4.19.1 General Purpose Inputs and Outputs (GPIO’s) .................................................... 69
4.19.2 Pulse Width Modulation (PWM) Back Light Control ............................................. 69
4.19.3 Low Power State .................................................................................................. 69
5. Electrical Specifications .......................................................................................................... 70
5.1 DC Characteristics............................................................................................................ 70
5.2 Preliminary AC Characteristics ......................................................................................... 72
6. Ordering Information ............................................................................................................... 76
7. Mechanical Specifications....................................................................................................... 77
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