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IDT71V67902S80PF Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT71V67902S80PF Datasheet(HTML) 1 Page - Integrated Device Technology |
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1 / 23 page  DECEMBER 2003 DSC-5317/08 1 ©2002 Integrated Device Technology, Inc. Pin Description Summary A0-A18 Address Inputs Input Synchronous CE Chip Enable Input Synchronous CS0, CS1 Chip Selects Input Synchronous OE Output Enable Input Asynchronous GW Global Write Enable Input Synchronous BWE Byte Write Enable Input Synchronous BW1, BW2, BW3, BW4(1) Individual Byte Write Selects Input Synchronous CLK Clock Input N/A ADV Burst Address Advance Input Synchronous ADSC Address Status (Cache Controller) Input Synchronous ADSP Address Status (Processor) Input Synchronous LBO Linear / Interleaved Burst Order Input DC ZZ Sleep Mode Input Asynchronous I/O0-I/O31, I/OP1-I/OP4 Data Input / Output I/O Synchronous VDD, VDDQ Core Power, I/O Power Supply N/A VSS Ground Supply N/A 5317 tbl 01 Features x 256K x 36, 512K x 18 memory configurations x x x x x Supports fast access times: – 7.5ns up to 117MHz clock frequency – 8.0ns up to 100MHz clock frequency – 8.5ns up to 87MHz clock frequency x LBO LBO LBO LBO LBO input selects interleaved or linear burst mode x x x x x Self-timed write cycle with global write control ( GW GW GW GW GW), byte write enable ( BWE BWE BWE BWE BWE), and byte writes (BW BW BW BW BWx) x x x x x 3.3V core power supply x x x x x Power down controlled by ZZ input x x x x x 2.5V I/O supply (VDDQ) x x x x x Packaged in a JEDEC Standard 100-pin thin plastic quad flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball grid array (fBGA). Description The IDT71V67702/7902 are high-speed SRAMs organized as 256K x 36/512K x 18. The IDT71V67702/7902 SRAMs contain write, NOTE: 1. BW3 and BW4 are not applicable for the IDT71V67902. 256K X 36, 512K X 18 3.3VSynchronousSRAMs 2.5V I/O, Burst Counter Flow-ThroughOutputs,SingleCycleDeselect IDT71V67702 IDT71V67902 data, address and control registers. There are no registers in the data outputpath(flow-througharchitecture). InternallogicallowstheSRAMto generate a self-timed write based upon a decision which can be left until the end of the write cycle. The burst mode feature offers the highest level of performance to the system designer, as the IDT71V67702/7902 can provide four cycles of dataforasingleaddresspresentedtotheSRAM. Aninternalburstaddress counter accepts the first cycle address from the processor, initiating the access sequence. The first cycle of output data will flow-through from the array after a clock-to-data access time delay from the rising clock edge of the same cycle. If burst mode operation is selected ( ADV=LOW), the subsequent three cycles of output data will be available to the user on the next three rising clock edges. The order of these three addresses are defined by the internal burst counter and the LBO input pin. TheIDT71V67702/7902SRAMsutilizeIDT’slatesthigh-performance CMOS process and are packaged in a JEDEC standard 14mm x 20mm 100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array (BGA) and a 165 fine pitch ball grid array (fBGA). |
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