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MT8889C Datasheet(PDF) 9 Page - Zarlink Semiconductor Inc |
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MT8889C Datasheet(HTML) 9 Page - Zarlink Semiconductor Inc |
9 / 31 page MT8889C 9 The adaptive micro interface provides access to five internal registers. The read-only Receive Data Register contains the decoded output of the last valid DTMF digit received. Data entered into the write-only Transmit Data Register will determine which tone pair is to be generated (see Table 1 for coding details). Transceiver control is accomplished with two control registers (see Tables 6 and 7), CRA and CRB, which have the same address. A write operation to CRB is executed by first setting the most significant bit (b3) in CRA. The following write operation to the same address will then be directed to CRB, and subsequent write cycles will be directed back to CRA. The read-only status register indicates the current transceiver state (see Table 8). A software reset must be included at the beginning of all programs to initialize the control registers upon power-up or power reset (see Figure 15). Refer to Tables 4-7 for bit descriptions of the two control registers. The multiplexed IRQ/CP pin can be programmed to generate an interrupt upon validation of DTMF signals or when the transmitter is ready for more data (burst mode only). Alternatively, this pin can be configured to provide a square-wave output of the call progress signal. The IRQ/CP pin is an open drain output and requires an external pull-up resistor (see Figure 13). Table 3. Internal Register Functions Table 4. CRA Bit Positions Table 5. CRB Bit Positions Motorola Intel RS0 R/W WR RD FUNCTION 00 0 1 Write to Transmit Data Register 01 1 0 Read from Receive Data Register 10 0 1 Write to Control Register 11 1 0 Read from Status Register b3 b2 b1 b0 RSEL IRQ CP/DTMF TOUT b3 b2 b1 b0 C/R S/D TEST BURST ENABLE Figure 12 a) & b) - MT8889 Interface Connections for Various Intel and Motorola Micros MC6800/6802 MT8889 MT8889C A0-A15 VMA D0-D3 RW MC68HC11 MC6809 MT8889 MT8889C 8031/8051 8080/8085 Φ2 CS RS0 D0-D3 R/W/WR DS/RD A8-A15 AS AD0-AD3 RW CS RS0 D0-D3 R/W/WR DS/RD DS A0-A15 Q E D0-D3 R/W CS RS0 D0-D3 R/W/WR DS/RD A8-A15 ALE P0 RD WR CS D0-D3 RS0 DS/RD R/W/WR (a) (b) |
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